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公开(公告)号：US06469334B2
公开(公告)日：2002-10-22
申请号：US09821596
申请日：2001-03-29
IPC分类号： H01L2994
CPC分类号： H01L28/56 , H01L21/28291 , H01L29/516 , H01L29/78391
摘要： A ferroelectric FET having an interface insulator layer containing ZrO2. The ferroelectric FET includes a gate oxide layer, the interface insulator layer is located on the gate oxide layer, and ferroelectric layered superlattice material is located on the interface insulator layer, The interface insulator layer has a thickness of from 15 to 25 nanometers.
摘要翻译： 具有含有ZrO 2的界面绝缘体层的铁电FET。 铁电FET包括栅极氧化物层，界面绝缘体层位于栅极氧化物层上，并且铁电层状超晶格材料位于界面绝缘体层上。界面绝缘体层的厚度为15至25纳米。
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2.发明授权Method for fabricating ferroelectric field effect transistor having an interface insulator layer formed by a liquid precursor 失效具有由液体前体形成的界面绝缘体的铁电场效应晶体管的制造方法公开(公告)号：US06255121B1
公开(公告)日：2001-07-03
申请号：US09258489
申请日：1999-02-26
IPC分类号： H01L2100
CPC分类号： H01L28/56 , H01L21/28291 , H01L29/516 , H01L29/78391
摘要： A method for forming an interface insulator layer in a ferroelectric FET memory, in which a liquid precursor is applied to a semiconductor substrate. Preferably, the liquid precursor is an enhanced metalorganic decomposition (“EMOD”) precursor, applied using a liquid-source misted deposition technique. Preferably, the EMOD precursor solution applied to the substrate contains metal ethylhexanoates containing metal moieties in relative molar proportions for forming an interface insulator layer containing ZrO2, CeO2, Y2O3 or (Ce1-xZrx)O2, wherein 0≦x≦1.
摘要翻译： 一种用于在铁电FET存储器中形成界面绝缘体层的方法，其中将液体前体施加到半导体衬底。 优选地，液体前体是使用液体源雾化沉积技术施加的增强的金属有机分解（“EMOD”）前体。 优选地，施加到基底上的EMOD前体溶液含有相对摩尔比例含有金属部分的金属乙基己酸，以形成含有ZrO 2，CeO 2，Y 2 O 3或（Ce 1-x Zr x）O 2的界面绝缘体层，其中0≤x≤1。
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公开(公告)号：US06541806B2
公开(公告)日：2003-04-01
申请号：US09229883
申请日：1999-01-14
IPC分类号： H01L27108
CPC分类号： H01L28/56 , H01L21/31691
摘要： A ferroelectric device includes a ferroelectric layer and an electrode. The ferroelectric material is made of a perovskite or a layered superlattice material. A superlattice generator metal oxide is deposited as a capping layer between said ferroelectric layer and said electrode to improve the residual polarization capacity of the ferroelectric layer.
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公开(公告)号：US06653156B2
公开(公告)日：2003-11-25
申请号：US10262034
申请日：2002-09-30
IPC分类号： H01L2100
CPC分类号： H01L28/56 , H01L21/31691
摘要： A ferroelectric device includes a ferroelectric layer and an electrode. The ferroelectric material is made of a perovskite or a layered superlattice material. A superlattice generator metal oxide is deposited as a capping layer between said ferroelectric layer and said electrode to improve the residual polarization capacity of the ferroelectric layer.
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公开(公告)号：US6151241A
公开(公告)日：2000-11-21
申请号：US314800
申请日：1999-05-19
IPC分类号： G11C11/22 , H01L21/336 , H01L29/51 , G11C11/00
CPC分类号： H01L29/6684 , G11C11/22 , H01L29/516
摘要： A ferroelectric field effect transistor memory cell includes a thin film varistor located between the gate electrode and the ferroelectric layer. The varistor protects the ferroelectric layer from disturb voltage pulses arising from memory read, write and sense operations. A second electrode is located between the thin film varistor and the ferroelectric layer. The thin film ferroelectric is positioned over the channel of a transistor to operate as a ferroelectric gate. For voltages at which disturb voltages are likely to occur, the thin film varistor has a resistance obeying a formula R.sub.d >10.times.1/(2.pi.fC.sub.F), where R.sub.d is resistivity of the thin film varistor, f is an operating frequency of said memory, and C.sub.F is the capacitance of the ferroelectric layer. For voltages at or near the read and write voltage of the memory, the thin film varistor has a resistance obeying a formula R.sub.d
摘要翻译： 铁电场效应晶体管存储单元包括位于栅电极和铁电层之间的薄膜变阻器。 压敏电阻保护铁电层不受存储器读，写和读操作引起的干扰电压脉冲的影响。 第二电极位于薄膜压敏电阻和铁电层之间。 薄膜铁电体位于晶体管的沟道上方，用作铁电栅极。 对于可能发生干扰电压的电压，薄膜压敏电阻具有遵循公式Rd> 10×1 /（2πfCF）的电阻，其中Rd是薄膜变阻器的电阻率，f是所述存储器的工作频率， CF是铁电层的电容。 对于等于或接近存储器的读和写电压的电压，薄膜压敏电阻具有遵循公式Rd <0.1x1 /（2πfCF）的电阻。
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6.发明授权Ferroelectric memory with ferroelectric thin film having thickness of 90 nanometers or less, and method of making same 有权具有厚度为90纳米或更小的铁电薄膜的铁电存储器及其制造方法
公开(公告)号：US6104049A
公开(公告)日：2000-08-15
申请号：US228578
申请日：1999-01-11
申请人： Narayan Solayappan , Vikram Joshi , Carlos A. Paz de Araujo , Larry D. McMillan , Shinichiro Hayashi , Tatsuo Otsuki
发明人： Narayan Solayappan , Vikram Joshi , Carlos A. Paz de Araujo , Larry D. McMillan , Shinichiro Hayashi , Tatsuo Otsuki
IPC分类号： G11C11/22 , H01L21/02 , H01L21/316 , H01L21/768 , H01L21/822 , H01L21/8242 , H01L21/8246 , H01L21/8247 , H01L27/04 , H01L27/10 , H01L27/105 , H01L27/108 , H01L27/115 , H01L29/788 , H01L29/792 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L27/11502 , H01L28/55 , H01L28/60 , H01L21/768
摘要： A coating of liquid precursor containing a metal is applied to a first electrode, baked on a hot plate in oxygen ambient at a temperature not exceeding 300.degree. C. for five minutes, then RTP annealed at 675.degree. C. for 30 seconds. The coating is then annealed in oxygen or nitrogen ambient at 700.degree. C. for one hour to form a thin film of layered superlattice material with a thickness not exceeding 90 nm. A second electrode is applied to form a capacitor, and a post-anneal is performed in oxygen or nitrogen ambient at a temperature not exceeding 700.degree. C. If the material is strontium bismuth tantalate, the precursor contains u mole-equivalents of strontium, v mole-equivalents of bismuth, and w mole-equivalents of tantalum, where 0.8.ltoreq.u.ltoreq.1.0, 2.0.ltoreq.v.ltoreq.2.3, and 1.9.ltoreq.w.ltoreq.2.1.
摘要翻译： 将包含金属的液体前体涂层施加到第一电极，在氧气环境中在不高于300℃的温度下在热板上烘烤五分钟，然后在675℃下进行RTP退火30秒。 然后将涂层在氧气或氮气环境中在700℃下退火1小时，以形成厚度不超过90nm的层状超晶格材料薄膜。 施加第二电极以形成电容器，并且在氧气或氮气环境中在不超过700℃的温度下进行后退火。如果该材料是钽酸铋锶，则该前体含有痣的锶，v 铋的摩尔当量和钽的摩尔当量，其中0.8为2.0，2.0
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7.发明授权Integrated circuit capacitors with barrier layer and process for making the same 失效具有阻挡层的集成电路电容器及其制造方法公开(公告)号：US06447838B1
公开(公告)日：2002-09-10
申请号：US08543827
申请日：1995-10-16
申请人： Masamichi Azuma , Eiji Fujii , Yasuhiro Uemoto , Shinichiro Hayashi , Toru Nasu , Yoshihiro Shimada , Akihiro Matsuda , Tatsuo Otsuki , Michael C. Scott , Joseph D. Cuchiaro , Carlos A. Paz de Araujo
发明人： Masamichi Azuma , Eiji Fujii , Yasuhiro Uemoto , Shinichiro Hayashi , Toru Nasu , Yoshihiro Shimada , Akihiro Matsuda , Tatsuo Otsuki , Michael C. Scott , Joseph D. Cuchiaro , Carlos A. Paz de Araujo
IPC分类号： B05D512
CPC分类号： H01L28/75 , H01L21/28568 , H01L28/55 , H01L28/65 , Y10T29/42
摘要： A Ti/TiN adhesion/barrier layer is formed on a substrate and annealed. The anneal step is performed at a temperature within a good morphology range of 100° C. above a base barrier anneal temperature that depends on the thickness of said barrier layer. The base barrier anneal temperature is about 700° C. for a barrier thickness of about 1000 Å and about 800° C. for a barrier thickness of about 3000 Å. The barrier layer is 800 Å thick or thicker. A first electrode is formed, followed by a BST dielectric layer and a second electrode. A bottom electrode structure in which a barrier layer of TiN is sandwiched between two layers of platinum is also disclosed. The process and structures also produce good results with other capacitor dielectrics, including ferroelectrics such as strontium bismuth tantalate.
摘要翻译： 在基板上形成Ti / TiN粘合/阻挡层并退火。 退火步骤在取决于所述阻挡层的厚度的基本阻挡退火温度之上的100℃的良好形态范围内进行。 对于约3000的屏障厚度，对于约1000和约800℃的阻挡层厚度，基底阻挡退火温度为约700℃。 阻挡层厚度为800或更厚。 形成第一电极，随后是BST介电层和第二电极。 还公开了其中TiN阻挡层夹在两层铂之间的底部电极结构。 该工艺和结构也与其他电容器电介质（包括铁电锶钽酸锶）等产生良好的结果。
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8.发明授权Method and apparatus for fabricating silicon dioxide and silicon glass layers in integrated circuits 失效用于在集成电路中制造二氧化硅和硅玻璃层的方法和装置
公开(公告)号：US5759923A
公开(公告)日：1998-06-02
申请号：US615806
申请日：1996-03-14
申请人： Larry D. McMillan , Michael C. Scott , Carlos A. Paz de Araujo , Tatsuo Otsuki , Shinichiro Hayashi
发明人： Larry D. McMillan , Michael C. Scott , Carlos A. Paz de Araujo , Tatsuo Otsuki , Shinichiro Hayashi
IPC分类号： B05D1/00 , B05D3/04 , B05D7/24 , C23C16/44 , C23C16/448 , C23C16/455 , C23C16/46 , C23C16/48 , C23C16/52 , C23C18/12 , C23C18/14 , C23C26/02 , C30B7/00 , H01L21/02 , H01L21/314 , H01L21/316 , H01L27/115 , H01L41/24 , H05K3/10 , H01L21/00
CPC分类号： H01L21/316 , B05D1/00 , B05D1/60 , B05D3/0493 , C23C16/4412 , C23C16/4486 , C23C16/45561 , C23C16/4558 , C23C16/46 , C23C16/482 , C23C16/52 , C23C18/1212 , C23C18/1287 , C23C18/14 , C23C26/02 , C30B29/68 , C30B7/00 , H01L21/314 , H01L21/31691 , H01L27/11502 , H01L28/56 , H01L28/60 , H01L41/316 , H01L28/55 , H05K3/105
摘要： A precursor liquid comprising silicon in a xylenes solvent is prepared, a substrate is placed within a vacuum deposition chamber, the precursor liquid is misted, and the mist is flowed into the deposition chamber while maintaining the chamber at ambient temperature to deposit a layer of the precursor liquid on the substrate. The liquid is dried, baked, and annealed to form a thin film of silicon dioxide or silicon glass on the substrate. Then an integrated circuit is completed to include at least a portion of the silicon dioxide or silicon glass layer as an insulator for an electronic device in the integrated circuit.
摘要翻译： 制备在二甲苯溶剂中包含硅的前体液体，将基底放置在真空沉积室内，使前体液体雾化，并将雾流入沉积室，同时将室保持在环境温度以沉积一层 前体液体在基底上。 将液体干燥，烘烤和退火以在基底上形成二氧化硅或硅玻璃的薄膜。 然后，完成集成电路以将至少一部分二氧化硅或硅玻璃层作为集成电路中的电子器件的绝缘体。
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公开(公告)号：US06198225B1
公开(公告)日：2001-03-06
申请号：US09326838
申请日：1999-06-07
申请人： Gota Kano , Yasuhiro Shimada , Shinichiro Hayashi , Koji Arita , Carlos A. Paz de Araujo , Joseph D. Cuchiaro , Larry D. McMillan
发明人： Gota Kano , Yasuhiro Shimada , Shinichiro Hayashi , Koji Arita , Carlos A. Paz de Araujo , Joseph D. Cuchiaro , Larry D. McMillan
IPC分类号： G09G310
CPC分类号： G09G3/367 , G09G3/22 , H01J1/30 , H01J2201/306 , H01J2329/00
摘要： A thin film of ferroelectric layered superlattice material in a flat panel display device is energized to selectively influence the display image. In one embodiment, a voltage pulse causes the layered superlattice material to emit electrons that impinge upon a phosphor, causing the phosphor to emit light. In another embodiment, an electric potential creates a remanent polarization in the layered superlattice material, which exerts an electric field in liquid crystal layer, thereby influencing the transmissivity of light through the liquid crystal. The layered superlattice material is a metal oxide formed using an inventive liquid precursor containing an alkoxycarboxylate. The thin film thickness is preferably in the range 50-140 nm, so that polarizabilty and transparency of the thin film is enhanced. A display element may comprise a varistor device to prevent cross-talk between pixels and to enable sudden polarization switching. A functional gradient in the ferroelectric thin film enhances electron emission. Two ferroelectric elements, one on either side of the phosphor may be used to enhance luminescence. A phosphor can be sandwiched between a dielectric and a ferroelectric to enhance emission.
摘要翻译： 平板显示装置中的铁电层状超晶格材料薄膜被通电以选择性地影响显示图像。 在一个实施例中，电压脉冲使得层状超晶格材料发射撞击磷光体的电子，导致磷光体发光。 在另一个实施例中，电位在层状超晶格材料中产生剩余极化，其在液晶层中施加电场，从而影响透过液晶的透射率。 层状超晶格材料是使用本发明的含有烷氧基羧酸盐的液体前体形成的金属氧化物。 薄膜厚度优选在50-140nm的范围内，从而提高薄膜的极化性和透明度。 显示元件可以包括用于防止像素之间的串扰并允许突发极化切换的变阻器装置。 铁电薄膜中的功能梯度增强了电子发射。 可以使用两个铁电元件，一个在荧光体的两侧，以增强发光。 荧光体可以夹在电介质和铁电体之间以增强发射。
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10.发明授权Method of forming magnesium oxide films on glass substrate for use in plasma display panels 失效在用于等离子体显示面板的玻璃基板上形成氧化镁膜的方法
公开(公告)号：US6017579A
公开(公告)日：2000-01-25
申请号：US838006
申请日：1997-04-14
申请人： Gota Kano , Carlos A. Paz De Araujo , Koji Arita , Michael C. Scott , Larry D. McMillan , Shinichiro Hayashi
发明人： Gota Kano , Carlos A. Paz De Araujo , Koji Arita , Michael C. Scott , Larry D. McMillan , Shinichiro Hayashi
CPC分类号： H01J9/20 , C03C17/25 , C03C2217/228 , C03C2218/11 , H01J2209/012 , H01J2211/40
摘要： A new method (P200) is provided for making magnesium oxide layers (122) in plasma displays (100). A magnesium carboxylate liquid precursor solution is applied to a display panel (102), dried, and annealed to yield a solid magnesium oxide layer (122) having excellent electro-optical performance.
摘要翻译： 提供了一种用于在等离子体显示器（100）中制造氧化镁层（122）的新方法（P200）。 将镁羧酸盐液体前体溶液施加到显示面板（102）上，干燥并退火，得到具有优异电光性能的固体氧化镁层（122）。
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