公开(公告)号：US10381363B2

公开(公告)日：2019-08-13

申请号：US14707749

申请日：2015-05-08

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Akira Goda ,  Durai Vishak Nirmal Ramaswamy

IPC: H01L29/788 ,  H01L27/1157 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/792 ,  H01L29/66 ,  H01L27/105 ,  H01L29/423

Abstract: A method for forming a string of memory cells, a memory device having a string of memory cells, and a system are disclosed. The string of memory cells can include a string of planar memory cells formed as recesses in each of a plurality of control gate material formed as a vertical stack of alternating insulator and control gate material. The recesses can be lined with a dielectric material and filled with a floating gate material. Metal nano-particles can be formed on a surface of the floating gate material and/or infused into the floating gate material.

公开(公告)号：US10355008B2

公开(公告)日：2019-07-16

申请号：US15980503

申请日：2018-05-15

Applicant: Micron Technology, Inc.

Inventor： Charles H. Dennison ,  Akira Goda ,  John Hopkins ,  Fatma Arzum Simsek-Ege ,  Krishna K. Parat

IPC: H01L27/11556 ,  H01L29/66 ,  H01L27/11578 ,  H01L21/28

Abstract: Floating gate memory cells in vertical memory. A control gate is formed between a first tier of dielectric material and a second tier of dielectric material. A floating gate is formed between the first tier of dielectric material and the second tier of dielectric material, wherein the floating gate includes a protrusion extending towards the control gate. A charge blocking structure is formed between the floating gate and the control gate, wherein at least a portion of the charge blocking structure wraps around the protrusion.

公开(公告)号：US20190088652A1

公开(公告)日：2019-03-21

申请号：US16183468

申请日：2018-11-07

Applicant: Micron Technology, Inc.

Inventor： Gloria Yang ,  Suraj J. Mathew ,  Raghunath Singanamalla ,  Vinay Nair ,  Scott J. Derner ,  Michael Amiel Shore ,  Brent Keeth ,  Fatma Arzum Simsek-Ege ,  Diem Thy N. Tran

IPC: H01L27/108 ,  H01L49/02 ,  H01L29/423 ,  G11C11/403 ,  H01L29/78 ,  H01L29/10 ,  H01L27/06 ,  H01L29/08 ,  H01L23/528

Abstract: Some embodiments include a memory cell having first and second transistors, and a capacitor vertically displaced relative to the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a source/drain region of the second transistor, and capacitor dielectric material between the first and second nodes. Some embodiments include a memory cell having first and second transistors vertically displaced relative to one another, and a capacitor between the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a source/drain region of the second transistor, and capacitor dielectric material between the first and second nodes.

公开(公告)号：US20180337195A1

公开(公告)日：2018-11-22

申请号：US16052123

申请日：2018-08-01

Applicant: Micron Technology, Inc.

Inventor： Srikant Jayanti ,  Fatma Arzum Simsek-Ege ,  Pavan Kumar Reddy Aella

IPC: H01L27/11582 ,  H01L29/788 ,  H01L21/02 ,  H01L29/66 ,  H01L29/51 ,  H01L29/16 ,  H01L29/04 ,  H01L27/11556 ,  H01L21/8239 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/28 ,  H01L27/11551 ,  H01L29/792

CPC classification number: H01L27/11582 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02274 ,  H01L21/0234 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/31111 ,  H01L21/32134 ,  H01L21/8239 ,  H01L27/11551 ,  H01L27/11556 ,  H01L29/04 ,  H01L29/16 ,  H01L29/511 ,  H01L29/518 ,  H01L29/66825 ,  H01L29/7883 ,  H01L29/7889 ,  H01L29/7926

Abstract: Semiconductor structures may include a stack of alternating dielectric materials and control gates, charge storage structures laterally adjacent to the control gates, a charge block material between each of the charge storage structures and the laterally adjacent control gates, and a pillar extending through the stack of alternating oxide materials and control gates. Each of the dielectric materials in the stack has at least two portions of different densities and/or different rates of removal. Also disclosed are methods of fabricating such semiconductor structures.

公开(公告)号：US20180331107A1

公开(公告)日：2018-11-15

申请号：US16033377

申请日：2018-07-12

Applicant: Micron Technology, Inc.

Inventor： Suraj J. Mathew ,  Kris K. Brown ,  Raghunath Singanamalla ,  Vinay Nair ,  Fawad Ahmed ,  Fatma Arzum Simsek-Ege ,  Diem Thy N. Tran

IPC: H01L27/108 ,  H01L29/94 ,  H01L27/06

CPC classification number: H01L27/108 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/10841 ,  H01L27/10864 ,  H01L28/60 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/7827 ,  H01L29/945

Abstract: Some embodiments include a memory cell having a first transistor supported by a semiconductor base, and having second and third transistors above the first transistor and vertically stacked one atop the other. Some embodiments include a memory cell having first, second and third transistors. The third transistor is above the second transistor, and the second and third transistors are above the first transistor. The first transistor has first and second source/drain regions, the second transistor has third and fourth source/drain regions, and the third transistor has fifth and sixth source/drain regions. A read bitline is coupled with the sixth source/drain region. A write bitline is coupled with the first source/drain region. A write wordline includes a gate of the first transistor. A read wordline includes a gate of the third transistor. A capacitor is coupled with the second source/drain region and with a gate of the second transistor.

公开(公告)号：US10103160B2

公开(公告)日：2018-10-16

申请号：US15013298

申请日：2016-02-02

Applicant: Micron Technology, Inc.

Inventor： Srikant Jayanti ,  Fatma Arzum Simsek-Ege ,  Pavan Kumar Reddy Aella

IPC: H01L27/115 ,  H01L29/788 ,  H01L27/11582 ,  H01L21/28 ,  H01L21/8239 ,  H01L21/311 ,  H01L27/11556 ,  H01L29/66 ,  H01L29/04 ,  H01L29/16 ,  H01L29/51 ,  H01L21/02 ,  H01L21/3213 ,  H01L29/792 ,  H01L27/11551

Abstract: Semiconductor structures may include a stack of alternating dielectric materials and control gates, charge storage structures laterally adjacent to the control gates, a charge block material between each of the charge storage structures and the laterally adjacent control gates, and a pillar extending through the stack of alternating oxide materials and control gates. Each of the dielectric materials in the stack has at least two portions of different densities and/or different rates of removal. Also disclosed are methods of fabricating such semiconductor structures.

公开(公告)号：US20180061837A1

公开(公告)日：2018-03-01

申请号：US15664217

申请日：2017-07-31

Applicant: Micron Technology, Inc.

Inventor： Suraj J. Mathew ,  Kris K. Brown ,  Raghunath Singanamalla ,  Vinay Nair ,  Fawad Ahmed ,  Fatma Arzum Simsek-Ege ,  Diem Thy N. Tran

IPC: H01L27/108 ,  H01L27/06 ,  H01L29/78 ,  H01L29/10 ,  H01L49/02 ,  H01L27/02

CPC classification number: H01L27/108 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/10841 ,  H01L27/10864 ,  H01L28/60 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/7827 ,  H01L29/945

Abstract: Some embodiments include a memory cell having a first transistor supported by a semiconductor base, and having second and third transistors above the first transistor and vertically stacked one atop the other. Some embodiments include a memory cell having first, second and third transistors. The third transistor is above the second transistor, and the second and third transistors are above the first transistor. The first transistor has first and second source/drain regions, the second transistor has third and fourth source/drain regions, and the third transistor has fifth and sixth source/drain regions. A read bitline is coupled with the sixth source/drain region. A write bitline is coupled with the first source/drain region. A write wordline includes a gate of the first transistor. A read wordline includes a gate of the third transistor. A capacitor is coupled with the second source/drain region and with a gate of the second transistor.

公开(公告)号：US09780102B2

公开(公告)日：2017-10-03

申请号：US14536021

申请日：2014-11-07

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Krishna K. Parat ,  Luan C. Tran ,  Meng-Wei Kuo ,  Yushi Hu

IPC: H01L29/788 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11556 ,  H01L21/822 ,  H01L27/11578 ,  H01L27/11529 ,  H01L27/1158

CPC classification number: H01L27/11524 ,  H01L21/8221 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/1158 ,  H01L27/11582

Abstract: Some embodiments include apparatuses and methods having a source material, a dielectric material over the source material, a select gate material over the dielectric material, a memory cell stack over the select gate material, a conductive plug located in an opening of the dielectric material and contacting a portion of the source material, and a channel material extending through the memory cell stack and the select gate material and contacting the conductive plug.

公开(公告)号：US09754952B2

公开(公告)日：2017-09-05

申请号：US14925589

申请日：2015-10-28

Applicant: Micron Technology, Inc.

Inventor： Charles H. Dennison ,  Akira Goda ,  John Hopkins ,  Fatma Arzum Simsek-Ege ,  Krishna K. Parat

IPC: H01L27/11556 ,  H01L29/66 ,  H01L27/11578 ,  H01L21/28

Abstract: Floating gate memory cells in vertical memory. A control gate is formed between a first tier of dielectric material and a second tier of dielectric material. A floating gate is formed between the first tier of dielectric material and the second tier of dielectric material, wherein the floating gate includes a protrusion extending towards the control gate. A charge blocking structure is formed between the floating gate and the control gate, wherein at least a portion of the charge blocking structure wraps around the protrusion.

公开(公告)号：US09559109B2

公开(公告)日：2017-01-31

申请号：US14746515

申请日：2015-06-22

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  John Hopkins ,  Srikant Jayanti

IPC: H01L29/792 ,  H01L27/115 ,  H01L29/66 ,  H01L29/788

CPC classification number: H01L27/11556 ,  H01L27/11524 ,  H01L27/11582 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

Abstract: Vertical memories and methods of making the same are discussed generally herein. In one embodiment, a vertical memory can include a vertical pillar extending to a source, an etch stop tier over the source, and a stack of alternating dielectric tiers and conductive tiers over the etch stop tier. The etch stop tier can comprise a blocking dielectric adjacent to the pillar. In another embodiment, the etch stop tier can comprise a blocking dielectric adjacent to the pillar, and a plurality of dielectric films horizontally extending from the blocking dielectric into the etch stop tier.

Abstract translation: 垂直记忆及其制备方法一般在此讨论。 在一个实施例中，垂直存储器可以包括延伸到源的垂直柱，源极上的蚀刻停止层，以及蚀刻停止层上方的交替介电层和导电层的堆叠。 蚀刻停止层可以包括邻近柱的阻挡电介质。 在另一个实施例中，蚀刻停止层可以包括邻近柱的阻挡电介质和从阻挡电介质水平延伸到蚀刻停止层中的多个电介质膜。