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    Methods of forming semiconductor devices with self-aligned contacts and low-k spacers and the resulting devices
    71.
    发明授权
    Methods of forming semiconductor devices with self-aligned contacts and low-k spacers and the resulting devices 有权
    形成具有自对准触点和低k间隔物的半导体器件的方法以及所得到的器件

    公开(公告)号：US08524592B1

    公开(公告)日：2013-09-03

    申请号：US13584055

    申请日：2012-08-13

    申请人： Ruilong Xie ,  Xiuyu Cai, Jr. ,  Kangguo Cheng ,  Ali Khakifirooz

    发明人： Ruilong Xie ,  Xiuyu Cai, Jr. ,  Kangguo Cheng ,  Ali Khakifirooz

    IPC分类号： H01L21/3205 ,  H01L21/4763

    CPC分类号： H01L29/78 ,  H01L21/76897 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636

    摘要： One illustrative method disclosed herein includes removing a portion of a sacrificial sidewall spacer to thereby expose at least a portion of the sidewalls of a sacrificial gate electrode and forming a liner layer on the exposed sidewalls of the sacrificial gate electrode. In this example, the method also includes forming a sacrificial gap fill material above the liner layer, exposing and removing the sacrificial gate electrode to thereby define a gate cavity that is laterally defined by the liner layer, forming a replacement gate structure, removing the sacrificial gap fill material and forming a low-k sidewall spacer adjacent the liner layer. A device is also disclosed that includes a gate cap layer, a layer of silicon nitride or silicon oxynitride positioned on each of two upstanding portions of a gate insulation layer and a low-k sidewall spacer positioned on the layer of silicon nitride or silicon oxynitride.

    摘要翻译： 本文公开的一种说明性方法包括去除牺牲侧壁间隔物的一部分，从而暴露牺牲栅电极的侧壁的至少一部分，并在牺牲栅电极的暴露的侧壁上形成衬垫层。 在该示例中，该方法还包括在衬垫层之上形成牺牲间隙填充材料，暴露和去除牺牲栅极电极，从而限定由衬里层横向限定的栅极腔，形成替代栅极结构，去除牺牲层 间隙填充材料并形成邻近衬层的低k侧壁间隔物。 还公开了一种器件，其包括栅极覆盖层，位于栅极绝缘层的两个直立部分中的每一个上的氮化硅或氮氧化硅层，以及位于氮化硅或氮氧化硅层上的低k侧壁间隔物。

    Extremely thin semiconductor-on-insulator (ETSOI) FET with a back gate and reduced parasitic capacitance
    73.
    发明授权
    Extremely thin semiconductor-on-insulator (ETSOI) FET with a back gate and reduced parasitic capacitance 有权
    极薄的绝缘体上半导体（ETSOI）FET，具有背栅极和降低的寄生电容

    公开(公告)号：US08507989B2

    公开(公告)日：2013-08-13

    申请号：US13108282

    申请日：2011-05-16

    申请人： Ali Khakifirooz ,  Kangguo Cheng ,  Bruce B. Doris

    发明人： Ali Khakifirooz ,  Kangguo Cheng ,  Bruce B. Doris

    IPC分类号： H01L27/12 ,  H01L29/786 ,  H01L29/66

    CPC分类号： H01L27/1203 ,  H01L21/764 ,  H01L21/84 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/78648 ,  H01L2029/42388

    摘要： An extremely thin SOI MOSFET device on an SOI substrate is provided with a back gate layer on a Si substrate superimposed by a thin BOX layer; an extremely thin SOI layer (ETSOI) on top of the thin BOX layer; and an FET device on the ETSOI layer having a gate stack insulated by spacers. The thin BOX is formed under the ETSOI channel, and is provided with a thicker dielectric under source and drain to reduce the source/drain to back gate parasitic capacitance. The thicker dielectric portion is self-aligned with the gate. A void within the thicker dielectric portion is formed under the source/drain region. The back gate is determined by a region of semiconductor damaged by implantation, and the formation of an insulating layer by lateral etch and back filling with dielectric.

    摘要翻译： 在SOI衬底上的非常薄的SOI MOSFET器件在Si衬底上设置有由薄BOX层叠加的背栅层; 在薄BOX层顶部的非常薄的SOI层（ETSOI）; 并且在ETSOI层上的FET器件具有由间隔物绝缘的栅极堆叠。 薄BOX形成在ETSOI通道下面，并在源极和漏极之间提供较厚的电介质，以减少源极/漏极到背栅极寄生电容。 较厚的电介质部分与栅极自对准。 较厚电介质部分内的空隙形成在源/漏区下。 背栅由通过注入损坏的半导体区域确定，并且通过横向蚀刻形成绝缘层并且用电介质反向填充。

    THIN HETEREOSTRUCTURE CHANNEL DEVICE
    76.
    发明申请
    THIN HETEREOSTRUCTURE CHANNEL DEVICE 有权
    薄型结构通道设备

    公开(公告)号：US20130161694A1

    公开(公告)日：2013-06-27

    申请号：US13607875

    申请日：2012-09-10

    申请人： Thomas N. Adam ,  Kangguo Cheng ,  Hong He ,  Ali Khakifirooz ,  Alexander Reznicek

    发明人： Thomas N. Adam ,  Kangguo Cheng ,  Hong He ,  Ali Khakifirooz ,  Alexander Reznicek

    IPC分类号： H01L21/8238 ,  H01L29/78 ,  H01L27/12

    CPC分类号： H01L21/02057 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/3065 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/1054

    摘要： A method of fabricating a semiconductor device that includes providing a substrate having at least a first semiconductor layer atop a dielectric layer, wherein the first semiconductor layer has a first thickness of less than 10 nm. The first semiconductor layer is etched with a halide based gas at a temperature of less than 675° C. to a second thickness that is less than the first thickness. A second semiconductor layer is epitaxially formed on an etched surface of the first semiconductor layer. A gate structure is formed directly on the second semiconductor layer. A source region and a drain region is formed on opposing sides of the gate structure.

    摘要翻译： 一种制造半导体器件的方法，其包括提供在电介质层顶部具有至少第一半导体层的衬底，其中所述第一半导体层具有小于10nm的第一厚度。 在小于675℃的温度下用卤化物基气体蚀刻第一半导体层至小于第一厚度的第二厚度。 在第一半导体层的蚀刻表面上外延形成第二半导体层。 栅极结构直接形成在第二半导体层上。 源极区域和漏极区域形成在栅极结构的相对侧上。

    Programmable anti-fuse structures with conductive material islands
    77.
    发明授权
    Programmable anti-fuse structures with conductive material islands 失效
    具有导电材料岛的可编程抗熔丝结构

    公开(公告)号：US08471356B2

    公开(公告)日：2013-06-25

    申请号：US12761780

    申请日：2010-04-16

    申请人： Kangguo Cheng ,  Louis L. Hsu ,  William R. Tonti ,  Chih-Chao Yang

    发明人： Kangguo Cheng ,  Louis L. Hsu ,  William R. Tonti ,  Chih-Chao Yang

    IPC分类号： G06F17/50 ,  H01L21/768 ,  H01L23/525

    CPC分类号： H01L23/5252 ,  G06F17/505 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Voltage programmable anti-fuse structures and methods are provided that include at least one conductive material island atop a dielectric surface that is located between two adjacent conductive features. In one embodiment, the anti-fuse structure includes a dielectric material having at least two adjacent conductive features embedded therein. At least one conductive material island is located on an upper surface of the dielectric material that is located between the at least two adjacent conductive features. A dielectric capping layer is located on exposed surfaces of the dielectric material, the at least one conductive material island and the at least two adjacent conductive features. When the anti-fuse structure is in a programmed state, a dielectric breakdown path is present in the dielectric material that is located beneath the at least one conductive material island which conducts electrical current to electrically couple the two adjacent conductive features.

    摘要翻译： 提供了电压可编程的抗熔丝结构和方法，其包括位于介于两个相邻导电特征之间的电介质表面上的至少一个导电材料岛。 在一个实施例中，反熔丝结构包括具有嵌入其中的至少两个相邻导电特征的电介质材料。 至少一个导电材料岛位于介电材料的位于至少两个相邻导电特征之间的上表面上。 电介质覆盖层位于电介质材料的暴露表面上，至少一个导电材料岛和至少两个相邻的导电特征。 当反熔丝结构处于编程状态时，介电击穿路径存在于介电材料中，介电材料位于至少一个导电材料岛之下，该导电材料岛传导电流以电耦合两个相邻导电特征。

    HIGH DENSITY MULTI-ELECTRODE ARRAY
    78.
    发明申请
    HIGH DENSITY MULTI-ELECTRODE ARRAY 审中-公开
    高密度多电极阵列

    公开(公告)号：US20130134546A1

    公开(公告)日：2013-05-30

    申请号：US13307608

    申请日：2011-11-30

    申请人： Kangguo Cheng ,  Arjang Hassibi ,  Ali Khakifirooz ,  Dharmendra S. Modha

    发明人： Kangguo Cheng ,  Arjang Hassibi ,  Ali Khakifirooz ,  Dharmendra S. Modha

    IPC分类号： H01L27/12 ,  H01L21/28

    CPC分类号： H01L27/1203 ,  A61B5/04001 ,  A61B2562/028 ,  A61B2562/046 ,  H01L21/76898

    摘要： A method includes forming one or more trenches in a substrate; lining the one or more trenches with a dielectric liner; filling the one or more trenches with a conductive electrode to form one or more trench electrodes; forming a transistor layer on the substrate; connecting each of the one or more trench electrodes to at least one access transistor in the transistor layer; and thinning the substrate to expose at least a portion of each of the trench electrodes.

    摘要翻译： 一种方法包括在衬底中形成一个或多个沟槽; 用介电衬垫衬一个或多个沟槽; 用导电电极填充一个或多个沟槽以形成一个或多个沟槽电极; 在所述基板上形成晶体管层; 将所述一个或多个沟槽电极中的每一个连接到所述晶体管层中的至少一个存取晶体管; 以及使基板变薄以暴露每个沟槽电极的至少一部分。