公开(公告)号：US08952528B2

公开(公告)日：2015-02-10

申请号：US13753930

申请日：2013-01-30

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chien-Feng Chan ,  Chun-Tang Lin ,  Yi Che Lai

IPC: H01L33/02 ,  H01L49/02 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L24/94 ,  H01L21/561 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L28/00 ,  H01L2224/0231 ,  H01L2224/12105 ,  H01L2224/13025 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16265 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92225 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2924/05432 ,  H01L2924/05442 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/141 ,  H01L2924/1421 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/18161 ,  H01L2924/19103 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor package is provided. The semiconductor package includes a semiconductor chip having opposite first and second surfaces; an RDL structure formed on the first surface of the semiconductor chip and having opposite third and fourth surfaces and a plurality of first conductive through holes penetrating the third and fourth surfaces thereof, wherein the RDL structure is formed on the semiconductor chip through the fourth surface thereof and electrically connected to the semiconductor chip through a plurality of first conductive elements, and the third surface of the RDL structure has a redistribution layer formed thereon; a plurality of conductive bumps formed on the redistribution layer; and an encapsulant formed on the first surface of the semiconductor chip for encapsulating the RDL structure, wherein the conductive bumps are embedded in and exposed from the encapsulant. The invention effectively prevents warpage of the semiconductor package and improves the electrical connection significantly.

Abstract translation: 提供半导体封装。 半导体封装包括具有相反的第一和第二表面的半导体芯片; 形成在半导体芯片的第一表面上并且具有相反的第三和第四表面的RDL结构以及穿过其第三和第四表面的多个第一导电通孔，其中RDL结构通过其第四表面形成在半导体芯片上 并通过多个第一导电元件与半导体芯片电连接，并且RDL结构的第三表面在其上形成再分布层; 形成在再分配层上的多个导电凸块; 以及密封剂，其形成在所述半导体芯片的用于封装所述RDL结构的所述第一表面上，其中所述导电凸块嵌入并暴露于所述密封剂。 本发明有效地防止了半导体封装的翘曲，并显着地改善了电连接。

公开(公告)号：US20140342505A1

公开(公告)日：2014-11-20

申请号：US14151153

申请日：2014-01-09

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD

Inventor： Yan-Heng Chen ,  Chun-Tang Lin ,  Mu-Hsuan Chan ,  Chieh-Yuan Chi ,  Yan-Yi Liao

IPC: H01L21/52 ,  H01L21/78

CPC classification number: H01L21/52 ,  H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/12105 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00

Abstract: A fabrication method of a semiconductor package is disclosed, which includes the steps of: providing a carrier; disposing at least a semiconductor element on the carrier; forming an encapsulant on the carrier and the semiconductor element for encapsulating the semiconductor element; removing the carrier; disposing a pressure member on the encapsulant; and forming an RDL structure on the semiconductor element and the encapsulant, thereby suppressing internal stresses through the pressure member so as to mitigate warpage on edges of the encapsulant.

Abstract translation: 公开了一种半导体封装的制造方法，其包括以下步骤：提供载体; 在载体上设置至少一个半导体元件; 在所述载体和所述半导体元件上形成用于封装所述半导体元件的密封剂; 移除载体; 将压力构件设置在密封剂上; 以及在半导体元件和密封剂上形成RDL结构，由此抑制通过压力构件的内部应力，从而减轻密封剂边缘的翘曲。

公开(公告)号：US20140127864A1

公开(公告)日：2014-05-08

申请号：US13730051

申请日：2012-12-28

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Kuan-Wei Chuang ,  Chun-Tang Lin ,  Yi-Che Lai

IPC: H01L21/58

CPC classification number: H01L24/80 ,  H01L21/568 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00

Abstract: A method of fabricating a semiconductor package is provided, including providing an interposer having a plurality of conductive elements, disposing the interposer on a carrier having a plurality of recessed portions for the conductive elements to be received therein such that the interposer is coupled to the carrier, attaching the semiconductor element to the interposer, and removing the carrier. Coupling the interposer to the carrier prevents the conductive elements from displacement under pressure. Therefore, the conductive elements will not be in poor or no electrical contact with the interposer.

Abstract translation: 提供一种制造半导体封装件的方法，包括提供具有多个导电元件的插入器，将该插入件设置在具有多个凹部的载体上，以便导电元件被接纳在其中，使得插入器耦合到载体 将半导体元件安装到插入件上，并移除载体。 将插入件耦合到载体可防止导电元件在压力下移位。 因此，导电元件不会变得不牢固，也不会与插入件电接触。

公开(公告)号：US20140077387A1

公开(公告)日：2014-03-20

申请号：US13682103

申请日：2012-11-20

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Kuan-Wei Chuang ,  Chun-Tang Lin ,  Yi-Chian Liao ,  Yi Che Lai

IPC: H01L23/48 ,  H01L21/50

CPC classification number: H01L23/481 ,  H01L21/50 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2224/81005 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/351 ,  H01L2224/81 ,  H01L2924/00

Abstract: A fabrication method of a semiconductor package is provided, which includes the steps of: cutting a substrate into a plurality of interposers; disposing the interposers on a carrier, wherein the interposers are spaced from one another by a distance; disposing at least a semiconductor element on each of the interposers; forming an encapsulant to encapsulate the interposers and the semiconductor elements; and removing the carrier. Therefore, by cutting the substrate first, good interposers can be selected and rearranged such that finished packages can be prevented from being wasted due to inferior interposers.

Abstract translation: 提供一种半导体封装的制造方法，其包括以下步骤：将衬底切割成多个中介层; 将所述插入件布置在载体上，其中所述插入件彼此间隔一定距离; 在每个所述插入件上设置至少一个半导体元件; 形成密封剂以封装所述插入件和所述半导体元件; 并移除载体。 因此，通过首先切割基板，可以选择和重新布置良好的插入件，从而可以防止成品封装因内插件不良而被浪费。

公开(公告)号：US20140070424A1

公开(公告)日：2014-03-13

申请号：US13722017

申请日：2012-12-20

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Kuan-Wei Chuang ,  Chun-Tang Lin ,  Yi-Chian Liao ,  Yi-Che Lai

IPC: H01L23/498 ,  H01L21/78

CPC classification number: H01L21/486 ,  H01L21/31111 ,  H01L21/4853 ,  H01L21/563 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/147 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49872 ,  H01L24/03 ,  H01L24/08 ,  H01L24/11 ,  H01L24/17 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/02317 ,  H01L2224/02372 ,  H01L2224/03002 ,  H01L2224/08235 ,  H01L2224/16 ,  H01L2224/16245 ,  H01L2924/351 ,  H01L2924/00

Abstract: A method of fabricating a semiconductor package is provided, including: cutting a substrate into a plurality of interposers; disposing the interposers in a plurality of openings of a carrier, wherein the openings are spaced from one another by a distance; forming a first encapsulant to encapsulate the interposers; removing the carrier; and disposing at least a semiconductor element on each of the interposers. By cutting the substrate first, good interposers can be selected and rearranged such that finished packages can be prevented from being wasted due to inferior interposers.

Abstract translation: 提供一种制造半导体封装的方法，包括：将衬底切割成多个中介层; 将所述插入件布置在载体的多个开口中，其中所述开口彼此间隔一定距离; 形成第一密封剂以封装所述插入件; 移除载体; 以及在每个所述插入件上设置至少一个半导体元件。 通过首先切割基板，可以选择和重新布置良好的插入件，从而可以防止由于不良插入件浪费完成的封装。

公开(公告)号：US20140008787A1

公开(公告)日：2014-01-09

申请号：US13677904

申请日：2012-11-15

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Chien-Feng Chan ,  Mu-Hsuan Chan ,  Chun-Tang Lin ,  Yi-Che Lai

IPC: H01L23/488 ,  H01L21/441

CPC classification number: H01L24/81 ,  H01L21/441 ,  H01L21/56 ,  H01L23/145 ,  H01L23/147 ,  H01L23/488 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/05572 ,  H01L2224/13022 ,  H01L2224/13084 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81805 ,  H01L2224/81815 ,  H01L2224/81986 ,  H01L2224/83104 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/9211 ,  H01L2224/92125 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/01047 ,  H01L2924/01029

Abstract: A conductive bump structure used to be formed on a substrate having a plurality of bonding pads. The conductive bump structure includes a first metal layer formed on the bonding pads, a second metal layer formed on the first metal layer, and a third metal layer formed on the second metal layer. The second metal layer has a second melting point higher than a third melting point of the third metal layer. Therefore, a thermal compression bonding process is allowed to be performed to the third metal layer first so as to bond the substrate to another substrate, and then a reflow process can be performed to melt the second metal layer and the third metal layer into each other so as to form an alloy portion, thus avoiding cracking of the substrate.

Abstract translation: 用于形成在具有多个接合焊盘的基板上的导电凸块结构。 导电凸块结构包括在接合焊盘上形成的第一金属层，形成在第一金属层上的第二金属层和形成在第二金属层上的第三金属层。 第二金属层的第二熔点高于第三金属层的第三熔点。 因此，首先对第三金属层进行热压接，从而将基板粘合到另一基板上，然后进行回流处理，使第二金属层和第三金属层彼此熔融 从而形成合金部分，从而避免基板的开裂。

公开(公告)号：US20130330883A1

公开(公告)日：2013-12-12

申请号：US13964465

申请日：2013-08-12

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Jung-Pang Huang ,  Hui-Min Huang ,  Kuan-Wei Chuang ,  Chun-Tang Lin ,  Yih-Jenn Jiang

IPC: H01L21/56

CPC classification number: H01L21/56 ,  H01L21/568 ,  H01L23/3121 ,  H01L23/36 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2924/014 ,  H01L2924/3511

Abstract: A semiconductor package includes: a chip having an active surface with a plurality of electrode pads and an inactive surface opposite to the active surface; an encapsulant encapsulating the chip and having opposite first and second surfaces, the first surface being flush with the active surface of the chip; and first and second metal layers formed on the second surface of the encapsulant, thereby providing a rigid support to the overall structure to prevent warpage and facilitating heat dissipation of the overall structure.

Abstract translation: 半导体封装包括：具有多个电极焊盘的有源表面和与该有源表面相对的无效表面的芯片; 密封剂，其封装所述芯片并且具有相对的第一和第二表面，所述第一表面与所述芯片的有源表面齐平; 以及形成在密封剂的第二表面上的第一和第二金属层，由此为整个结构提供刚性支撑以防止翘曲并促进整体结构的散热。