公开(公告)号：US20180047849A1

公开(公告)日：2018-02-15

申请号：US15723149

申请日：2017-10-02

Applicant: STMICROELECTRONICS, INC.

Inventor： Qing Liu ,  John H. Zhang

IPC: H01L29/788 ,  H01L29/66 ,  H01L27/088

CPC classification number: H01L29/7883 ,  H01L27/088 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/7889

Abstract: A semi-floating gate transistor is implemented as a vertical FET built on a silicon substrate, wherein the source, drain, and channel are vertically aligned, on top of one another. Current flow between the source and the drain is influenced by a control gate and a semi-floating gate. Front side contacts can be made to each one of the source, drain, and control gate terminals of the vertical semi-floating gate transistor. The vertical semi-floating gate FET further includes a vertical tunneling FET and a vertical diode. Fabrication of the vertical semi-floating gate FET is compatible with conventional CMOS manufacturing processes, including a replacement metal gate process. Low-power operation allows the vertical semi-floating gate FET to provide a high current density compared with conventional planar devices.

公开(公告)号：US09887196B2

公开(公告)日：2018-02-06

申请号：US14583842

申请日：2014-12-29

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc. ,  STMicroelectronics, Inc.

Inventor： Xiuyu Cai ,  Qing Liu ,  Ruilong Xie ,  Chun-chen Yeh

IPC: H01L27/092 ,  H01L29/10 ,  H01L27/12 ,  H01L21/84 ,  H01L29/165 ,  H01L21/308 ,  H01L21/8238 ,  H01L29/16 ,  H01L29/06 ,  H01L21/033 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0922 ,  H01L27/1211 ,  H01L29/0684 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/165 ,  H01L29/7849

Abstract: A semiconductor substrate includes a bulk substrate layer that extends along a first axis to define a width and a second axis perpendicular to the first axis to define a height. A plurality of hetero semiconductor fins includes an epitaxial material formed on a first region of the bulk substrate layer. A plurality of non-hetero semiconductor fins is formed on a second region of the bulk substrate layer different from the first region. The non-hetero semiconductor fins are integrally formed from the bulk substrate layer such that the material of the non-hetero semiconductor fins is different from the epitaxial material.

公开(公告)号：US09685555B2

公开(公告)日：2017-06-20

申请号：US14584161

申请日：2014-12-29

Applicant: STMICROELECTRONICS, INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Qing Liu ,  Nicolas Loubet ,  Chun-chen Yeh ,  Ruilong Xie ,  Xiuyu Cai

IPC: H01L29/49 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L21/768

CPC classification number: H01L29/7856 ,  H01L21/76816 ,  H01L21/76897 ,  H01L29/0657 ,  H01L29/4975 ,  H01L29/6681 ,  H01L2029/7858

Abstract: Tapered source and drain contacts for use in an epitaxial FinFET prevent short circuits and damage to parts of the FinFET during contact processing, thus improving device reliability. The inventive contacts feature tapered sidewalls and a pedestal where electrical contact is made to fins in the source and drain regions. The pedestal also provides greater contact area to the fins, which are augmented by extensions. Raised isolation regions define a valley around the fins. During source/drain contact formation, the valley is lined with a conformal barrier that also covers the fins themselves. The barrier protects underlying local oxide and adjacent isolation regions against gouging while forming the contact. The valley is filled with an amorphous silicon layer that protects the epitaxial fin material from damage during contact formation. A simple tapered structure is used for the gate contact.

公开(公告)号：US09685380B2

公开(公告)日：2017-06-20

申请号：US13907613

申请日：2013-05-31

Applicant: STMicroelectronics, Inc.

Inventor： Nicolas Loubet ,  Prasanna Khare ,  Qing Liu

IPC: H01L21/8238 ,  H01L27/092 ,  H01L21/3065 ,  H01L21/308

CPC classification number: H01L21/823807 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0922

Abstract: A method for co-integrating finFETs of two semiconductor material types, e.g., Si and SiGe, on a bulk substrate is described. Fins for finFETs may be formed in an epitaxial layer of a first semiconductor type, and covered with an insulator. A portion of the fins may be removed to form voids in the insulator, and the voids may be filled by epitaxially growing a semiconductor material of a second type in the voids. The co-integrated finFETs may be formed at a same device level.

公开(公告)号：US09640633B1

公开(公告)日：2017-05-02

申请号：US14974589

申请日：2015-12-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc. ,  STMicroelectronics, Inc.

Inventor： Andrew M. Greene ,  Qing Liu ,  Ruilong Xie ,  Chun-Chen Yeh

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L21/306

CPC classification number: H01L29/66545 ,  H01L21/76224 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823475 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/66515 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device that includes a first fin structure in a first portion of a substrate, and a second fin structure in a second portion of the substrate, wherein the first portion of the substrate is separated from the second portion of the substrate by at least one isolation region. A gate structure present extending from the first fin structure across the isolation region to the second fin structure. The gate structure including a first portion on the first fin structure including a first work function metal having at least one void, an isolation portion that is voidless present overlying the isolation region, and a second portion on the second fin structure including a second work function metal.

公开(公告)号：US09633911B2

公开(公告)日：2017-04-25

申请号：US14668482

申请日：2015-03-25

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMicroelectronics, Inc. ,  GLOBALFOUNDRIES Inc.

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Qing Liu ,  Nicolas Loubet ,  Scott Luning

IPC: H01L43/02 ,  H01L43/08 ,  H01L43/12 ,  H01L27/22 ,  H01L43/10 ,  H01L21/84 ,  H01L27/12 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/49 ,  H01L29/10 ,  H01L29/16 ,  H01L29/161

CPC classification number: H01L21/845 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/84 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/4966

Abstract: A method for semiconductor fabrication includes providing channel regions on a substrate including at least one Silicon Germanium (SiGe) channel region, the substrate including a plurality of regions including a first region and a second region. Gate structures are formed for a first n-type field effect transistor (NFET) and a first p-type field effect transistor (PFET) in the first region and a second NFET and a second PFET in the second region, the gate structure for the first PFET being formed on the SiGe channel region. The gate structure for the first NFET includes a gate material having a first work function and the gate structures for the first PFET, second NFET and second PFET include a gate material having a second work function such that multi-threshold voltage devices are provided.

公开(公告)号：US09570512B2

公开(公告)日：2017-02-14

申请号：US14960595

申请日：2015-12-07

Applicant: STMicroelectronics, Inc.

Inventor： Qing Liu ,  John Hongguang Zhang

IPC: H01L21/4763 ,  H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2436 ,  H01L23/528 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1616 ,  H01L45/1633 ,  H01L45/1691

Abstract: A resistive random access memory (RRAM) structure is formed on a supporting substrate and includes a first electrode and a second electrode. The first electrode is made of a silicided fin on the supporting substrate and a first metal liner layer covering the silicided fin. A layer of dielectric material having a configurable resistive property covers at least a portion of the first metal liner. The second electrode is made of a second metal liner layer covering the layer of dielectric material and a metal fill in contact with the second metal liner layer. A non-volatile memory cell includes the RRAM structure electrically connected between an access transistor and a bit line.

Abstract translation: 在支撑衬底上形成电阻随机存取存储器（RRAM）结构，并且包括第一电极和第二电极。 第一电极由支撑衬底上的硅化物翅片和覆盖硅化物翅片的第一金属衬垫层制成。 具有可配置电阻性能的电介质材料层覆盖第一金属衬垫的至少一部分。 第二电极由覆盖电介质材料层的第二金属衬垫层和与第二金属衬垫层接触的金属填充物制成。 非易失性存储单元包括电连接在存取晶体管和位线之间的RRAM结构。

公开(公告)号：US20160365456A1

公开(公告)日：2016-12-15

申请号：US14739634

申请日：2015-06-15

Applicant: STMicroelectronics, Inc.

Inventor： Qing Liu ,  John H. Zhang

IPC: H01L29/788 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L29/7883 ,  H01L27/088 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/7889

Abstract: A semi-floating gate transistor is implemented as a vertical FET built on a silicon substrate, wherein the source, drain, and channel are vertically aligned, on top of one another. Current flow between the source and the drain is influenced by a control gate and a semi-floating gate. Front side contacts can be made to each one of the source, drain, and control gate terminals of the vertical semi-floating gate transistor. The vertical semi-floating gate FET further includes a vertical tunneling FET and a vertical diode. Fabrication of the vertical semi-floating gate FET is compatible with conventional CMOS manufacturing processes, including a replacement metal gate process. Low-power operation allows the vertical semi-floating gate FET to provide a high current density compared with conventional planar devices.

Abstract translation: 半浮栅晶体管被实现为内置于硅衬底上的垂直FET，其中源极，漏极和沟道彼此垂直对准。 源极和漏极之间的电流流动受到控制栅极和半浮栅的影响。 可以对垂直半浮栅晶体管的源极，漏极和控制栅极端子中的每一个进行正面接触。 垂直半浮栅FET还包括垂直隧道FET和垂直二极管。 垂直半浮栅FET的制造与常规CMOS制造工艺兼容，包括替代金属栅极工艺。 与传统的平面器件相比，低功耗操作允许垂直半浮栅FET提供高电流密度。

公开(公告)号：US20160322479A1

公开(公告)日：2016-11-03

申请号：US14698921

申请日：2015-04-29

Applicant: STMicroelectronics, Inc.

Inventor： Qing Liu ,  Salih Muhsin Celik

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/51 ,  H01L29/165 ,  H01L29/78

CPC classification number: H01L29/66977 ,  H01L29/0649 ,  H01L29/083 ,  H01L29/0834 ,  H01L29/165 ,  H01L29/4941 ,  H01L29/513 ,  H01L29/516 ,  H01L29/66356 ,  H01L29/7391 ,  H01L29/7851

Abstract: A tunneling field effect transistor is formed from a fin of semiconductor material on a support substrate. The fin of semiconductor material includes a source region, a drain region and a channel region between the source region and drain region. A gate electrode straddles over the fin at the channel region. Sidewall spacers are provided on each side of the gate electrode. The source of the transistor is made from an epitaxial germanium content source region grown from the source region of the fin and doped with a first conductivity type. The drain of the transistor is made from an epitaxial silicon content drain region grown from the drain region of the fin and doped with a second conductivity type.

Abstract translation: 隧道场效应晶体管由支撑基板上的半导体材料的翅片形成。 半导体材料的鳍片包括源极区域，漏极区域和源极区域与漏极区域之间的沟道区域。 栅极电极横跨在通道区域上的翅片上。 在栅电极的每一侧设置侧壁间隔物。 晶体管的源极由从鳍片的源极区域生长并掺杂有第一导电类型的外延锗含量源区域制成。 晶体管的漏极由从鳍片的漏极区域生长并掺杂有第二导电类型的外延硅含量漏极区域制成。

公开(公告)号：US20160284607A1

公开(公告)日：2016-09-29

申请号：US14670800

申请日：2015-03-27

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES, Inc. ,  STMICROELECTRONICS, INC.

Inventor： Xiuyu Cai ,  Qing Liu ,  Ruilong Xie ,  Chun-Chen Yeh

IPC: H01L21/84 ,  H01L29/78 ,  H01L27/12

CPC classification number: H01L21/845 ,  H01L27/1211 ,  H01L29/7849

Abstract: Fabricating a semiconductor device includes providing a strained semiconductor material (SSM) layer disposed on a dielectric layer, forming a first plurality of fins on the SSOI structure, at least one fin of the first plurality of fins is in a nFET region and at least one fin is in a pFET region, etching portions of the dielectric layer under portions of the SSM layer of the at least one fin in the pFET region, filling areas cleared by the etching, forming a second plurality of fins from the at least one fin in the nFET region such that each fin comprises a portion of the SSM layer disposed on the dielectric layer, and forming a third plurality of fins from the at least one fin in the pFET region such that each fin comprises a portion of the SSM layer disposed on a flowable oxide.

Abstract translation: 制造半导体器件包括提供设置在电介质层上的应变半导体材料（SSM）层，在SSOI结构上形成第一多个鳍片，第一组多个鳍片中的至少一个鳍片在nFET区域中，并且至少一个 鳍状物在pFET区域中，在pFET区域中的至少一个鳍片的SSM层的部分之下蚀刻介电层的部分，通过蚀刻清除的填充区域，从至少一个鳍片形成第二多个鳍片 所述nFET区域使得每个鳍片包括设置在所述电介质层上的所述SSM层的一部分，以及从所述pFET区域中的所述至少一个翅片形成第三多个翅片，使得每个翅片包括设置在所述SSM层上的部分 可流动的氧化物。