公开(公告)号：US20060035409A1

公开(公告)日：2006-02-16

申请号：US11212015

申请日：2005-08-24

申请人： Daewoong Suh ,  Debendra Mallik

发明人： Daewoong Suh ,  Debendra Mallik

IPC分类号： H01L21/58

CPC分类号： H01L23/3128 ,  H01L23/49816 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Methods and apparatuses to provide a stacked-die device comprised of stacked sub-packages. For one embodiment of the invention, each sub-package has interconnections formed on the die-side of the substrate for interconnecting to another sub-package. The dies and associated wires are protected by an encapsulant leaving an upper portion of each interconnection exposed. For one embodiment of the invention the encapsulant is a stencil-printable encapsulant and the upper portion of the interconnection is exposed by use of a patterned stencil during application of the encapsulant.

摘要翻译： 提供由堆叠的子包装组成的堆叠管芯装置的方法和装置。 对于本发明的一个实施例，每个子封装具有形成在衬底的裸片侧上的互连，用于互连到另一个子封装。 模具和相关电线由密封剂保护，留下每个互连的上部部分。 对于本发明的一个实施例，密封剂是模版印刷的密封剂，并且在施加密封剂期间通过使用图案化的模板来暴露互连的上部。

公开(公告)号：US06992891B2

公开(公告)日：2006-01-31

申请号：US10406721

申请日：2003-04-02

申请人： Debendra Mallik ,  Christopher L. Rumer ,  Jeffrey S. Winton ,  Michele J. Berry

发明人： Debendra Mallik ,  Christopher L. Rumer ,  Jeffrey S. Winton ,  Michele J. Berry

IPC分类号： H05K7/20

CPC分类号： H01L23/427 ,  H01L21/563 ,  H01L23/36 ,  H01L23/38 ,  H01L23/473 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/16152 ,  H01L2924/00

摘要： An assembly including a heat dissipation device having an attachment surface, a substrate having an attachment surface, and a plurality of metal balls extending between the heat dissipation device attachment surface and the substrate attachment surface. The assembly may include at least one microelectronic die disposed between the heat dissipation device attachment surface and the substrate attachment surface.

摘要翻译： 一种组件，包括具有附接表面的散热装置，具有附接表面的基板和在散热装置附接表面和基板附接表面之间延伸的多个金属球。 组件可以包括设置在散热装置附接表面和基板附接表面之间的至少一个微电子管芯。

公开(公告)号：US20060006535A1

公开(公告)日：2006-01-12

申请号：US11227532

申请日：2005-09-14

申请人： Dustin Wood ,  Debendra Mallik

发明人： Dustin Wood ,  Debendra Mallik

IPC分类号： H01L21/44 ,  H01L23/48

CPC分类号： H01L23/498 ,  H01L21/4846 ,  H01L2224/16225 ,  H01L2924/3011 ,  H05K3/242 ,  H05K3/243 ,  H05K2201/0391 ,  H05K2201/094 ,  H05K2203/072 ,  H05K2203/0723 ,  H05K2203/073

摘要： In one embodiment, a method including providing a semiconductor pad package having a first pad and a second pad is disclosed. A first layer comprising a first metal is deposited on the first pad using a first process. A second metal is then deposited on the first pad and the first layer using a second process. In another embodiment, the first process comprises and electroplating process, and the second process comprises a direct immersion gold (DIG) process. In a further embodiment, the first pad is a power or ground pad, and the second pad is a signal pad.

摘要翻译： 在一个实施例中，公开了一种包括提供具有第一焊盘和第二焊盘的半导体焊盘封装的方法。 使用第一工艺将包含第一金属的第一层沉积在第一焊盘上。 然后使用第二工艺将第二金属沉积在第一焊盘和第一层上。 在另一个实施例中，第一工艺包括电镀工艺，第二工艺包括直接浸金（DIG）工艺。 在另一实施例中，第一焊盘是电源或接地焊盘，第二焊盘是信号焊盘。

公开(公告)号：US20050112880A1

公开(公告)日：2005-05-26

申请号：US10685171

申请日：2003-10-13

申请人： Dustin Wood ,  Debendra Mallik

发明人： Dustin Wood ,  Debendra Mallik

IPC分类号： H01L21/48 ,  H01L23/498 ,  H05K3/24 ,  H01L21/302 ,  H01L21/461

CPC分类号： H01L23/498 ,  H01L21/4846 ,  H01L2224/16225 ,  H01L2924/3011 ,  H05K3/242 ,  H05K3/243 ,  H05K2201/0391 ,  H05K2201/094 ,  H05K2203/072 ,  H05K2203/0723 ,  H05K2203/073

摘要： In one embodiment, a method including providing a semiconductor pad package having a first pad and a second pad is disclosed. A first layer comprising a first metal is deposited on the first pad using a first process. A second metal is then deposited on the first pad and the first layer using a second process. In another embodiment, the first process comprises and electroplating process, and the second process comprises a direct immersion gold (DIG) process. In a further embodiment, the first pad is a power or ground pad, and the second pad is a signal pad.

摘要翻译： 在一个实施例中，公开了一种包括提供具有第一焊盘和第二焊盘的半导体焊盘封装的方法。 使用第一工艺将包含第一金属的第一层沉积在第一焊盘上。 然后使用第二工艺将第二金属沉积在第一焊盘和第一层上。 在另一个实施例中，第一工艺包括电镀工艺，第二工艺包括直接浸金（DIG）工艺。 在另一实施例中，第一焊盘是电源或接地焊盘，第二焊盘是信号焊盘。

公开(公告)号：US06821823B2

公开(公告)日：2004-11-23

申请号：US10744316

申请日：2003-12-22

申请人： Hong Xie ,  Debendra Mallik

发明人： Hong Xie ,  Debendra Mallik

IPC分类号： H01L2144

CPC分类号： H01L23/16 ,  H01L2224/16225 ,  H01L2924/19105 ,  H05K1/0231 ,  H05K1/0271 ,  H05K3/284 ,  H05K2201/2009

摘要： A molded stiffener for a package substrate is presented. The stiffener includes a molded portion. The molded portion is molded of an electrically nonconductive molding compound. A plurality of capacitors are embedded in the molded portion. The capacitors are constructed and arranged to be electrically connected to the package substrate. As such, power delivery performance is improved, and mechanical strength is added to the substrate.

公开(公告)号：US5844316A

公开(公告)日：1998-12-01

申请号：US873312

申请日：1997-06-11

申请人： Debendra Mallik ,  Joni Hansen ,  Ashok K. Seth ,  Neil R. Sugai

发明人： Debendra Mallik ,  Joni Hansen ,  Ashok K. Seth ,  Neil R. Sugai

IPC分类号： H01L21/48 ,  H01L23/498 ,  H05K3/34 ,  H01L23/48

CPC分类号： H05K3/3478 ,  H01L21/4853 ,  H01L23/49816 ,  H01L2924/0002 ,  H05K2203/041 ,  H05K2203/0485 ,  H05K2203/0557 ,  H05K2203/082 ,  H05K3/3489

摘要： Methods for soldering a ball grid array (BGA) integrated circuit package to a printed circuit board. One method includes the steps of applying a solder flux to the conductive surface pads of a printed circuit board and capturing a plurality of solder balls with a separate fixture. The fixture is then placed onto the printed circuit board and the solder balls are released onto the conductive surface pads. The fixture is removed and an integrated circuit package is placed onto the solder balls. Solder flux may be applied to the bottom of the package to adhere the package to the balls. The solder balls are then reflowed to attach the package to the board. The flux provides a bonding agent which maintains the position of the solder balls and package while the solder is being reflowed. Another method includes the step of placing a fixture adjacent to the integrated circuit package so that a plurality of openings in the fixture are aligned with surface pads located on the bottom surface of the package. Solder balls are then placed into the fixture holes, adjacent to the surface pads of the package. The solder is then reflowed and the fixture is removed so that the package and solder balls can be subsequently soldered to a printed circuit board.

摘要翻译： 将球栅阵列（BGA）集成电路封装焊接到印刷电路板的方法。 一种方法包括以下步骤：将焊剂施加到印刷电路板的导电表面焊盘并且用单独的夹具捕获多个焊球。 然后将夹具放置在印刷电路板上，并将焊球释放到导电表面焊盘上。 去除固定装置，并将集成电路封装放置在焊球上。 可以将焊剂焊接到封装的底部，以将封装粘附到球上。 然后将焊球回流以将封装附接到板上。 焊剂提供一种粘合剂，其在焊料被回流时保持焊球和包装的位置。 另一种方法包括将夹具放置在集成电路封装附近的步骤，使得夹具中的多个开口与位于封装的底表面上的表面焊盘对齐。 然后将焊球放置在与封装的表面焊盘相邻的固定孔中。 然后将焊料回流并去除夹具，使得封装和焊球可以随后焊接到印刷电路板。

公开(公告)号：US5557502A

公开(公告)日：1996-09-17

申请号：US399162

申请日：1995-03-02

申请人： Koushik Banerjee ,  Debendra Mallik ,  Ashok Seth

发明人： Koushik Banerjee ,  Debendra Mallik ,  Ashok Seth

IPC分类号： H05K7/20 ,  H01L23/12 ,  H01L23/13 ,  H01L23/14 ,  H01L23/36 ,  H01L23/498 ,  H01L23/64 ,  H01L25/00 ,  H05K1/02 ,  H05K1/11

CPC分类号： H01L23/642 ,  H01L23/13 ,  H01L23/142 ,  H01L23/36 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/49 ,  H05K1/114 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49109 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/1532 ,  H01L2924/16195 ,  H01L2924/19041 ,  H01L2924/30107 ,  H05K1/0201 ,  H05K2201/10719 ,  H05K2201/10734 ,  H05K2201/10969 ,  H05K2203/0455

摘要： An integrated circuit package which has internal bonding pads that are located on bonding shelves and coupled to internal conductive power/ground planes by conductive strips that extend along the edges of the shelves. The edge strips eliminate the need for conventional vias to couple the bonding pads to the planes and thus reduce the cost and size of the package and improve package electrical performance (less inductive, less resistance path). The bonding pads are coupled to an integrated circuit that is mounted to a heat slug attached to a top surface of the package. The heat slug can function as both a ground path and a thermal sink for the integrated circuit. The package may have capacitors coupled to the internal routing of the package to reduce the electrical noise of the signals provided to the integrated circuit. Additionally, the package may have multiple power planes dedicated to different voltage levels. The bonding pads and conductive planes are coupled to landing pads located on a bottom surface of the package. Attached to the landing pads are solder balls which can be soldered to an external printed circuit board.

摘要翻译： 一种集成电路封装，其具有位于结合搁架上并具有沿着搁架边缘延伸的导电条连接到内部导电电源/接地层的内部接合焊盘。 边缘条消除了对传统通孔的需要，以将接合焊盘耦合到平面，从而降低封装的成本和尺寸并提高封装电性能（较小的电感，较小的电阻路径）。 接合焊盘耦合到集成电路，该集成电路安装到附接到封装的顶表面的散热片。 散热片可用作集成电路的接地路径和散热片。 封装可以具有耦合到封装的内部布线的电容器，以减少提供给集成电路的信号的电噪声。 此外，封装可以具有专用于不同电压电平的多个电源层。 接合焊盘和导电平面耦合到位于封装的底表面上的着陆焊盘。 连接到着陆焊盘的是可以焊接到外部印刷电路板的焊球。

公开(公告)号：US5556807A

公开(公告)日：1996-09-17

申请号：US140070

申请日：1994-06-14

申请人： Bidyut K. Bhattacharyya ,  Debendra Mallik ,  Syunsuke Ban ,  Takatoshi Takikawa ,  Shosaku Yamanaka

发明人： Bidyut K. Bhattacharyya ,  Debendra Mallik ,  Syunsuke Ban ,  Takatoshi Takikawa ,  Shosaku Yamanaka

IPC分类号： C23C14/06 ,  C23C14/14 ,  H01L23/485 ,  H01L23/495 ,  H01L23/50 ,  H01L23/64 ,  H01L21/60

CPC分类号： H01L23/495 ,  H01L23/49527 ,  H01L23/49534 ,  H01L23/49537 ,  H01L23/49589 ,  H01L23/642 ,  H01L23/647 ,  H01L24/49 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/49109 ,  H01L2224/73265 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01052 ,  H01L2924/01057 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/04953 ,  H01L2924/10253 ,  H01L2924/12033 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/16195 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  Y10S257/904

摘要： A method and resulting structure for constructing an IC package utilizing thin film technology. The package has a bottom conductive plate that has a layer of ceramic vapor deposited onto the plate in a predetermined pattern. Adjacent to the insulative layer of ceramic is a layer of conductive metal vapor deposited onto the ceramic. The layer of metal can be laid down onto the ceramic in a predetermined pattern to create a power plane, a plurality of signal lines, or a combination of power planes and signal lines. On top of the layer of conductive material is a lead frame separated by a layer of insulative polyimide material. The polyimide material has a plurality of holes filled with a conductive material, which electrically couple the layer of conductive material with the leads of the lead frame. The power and ground pads of the integrated circuit are connected to the layer of vapor deposited conductive material and conductive plate, which are also coupled to the corresponding leads of the lead frame, thereby connecting the IC to the leads of the lead frame. The signal pads of the IC are connected to the lead frame and/or signal lines formed within the layer of vapor deposited conductive material. The IC and attached circuit package can then be encapsulated in a plastic shell.

摘要翻译： PCT No.PCT / US93 / 01481 Sec。 371日期：1994年6月14日 102（e）日期1994年6月14日PCT提交1993年2月18日PCT公布。 WO93 / 16492 PCT出版物 日期1993年9月19日利用薄膜技术构建IC封装的方法和结果。 封装具有底部导电板，其具有以预定图案沉积在板上的陶瓷气相层。 与陶瓷绝缘层相邻的是沉积在陶瓷上的导电金属蒸气层。 可以以预定图案将金属层放置在陶瓷上以产生电力平面，多条信号线或电力平面和信号线的组合。 在导电材料层的顶部是由绝缘聚酰亚胺材料层隔开的引线框架。 聚酰亚胺材料具有填充有导电材料的多个孔，其将导电材料层与引线框架的引线电耦合。 集成电路的电源和接地焊盘连接到蒸镀导电材料层和导电板，该层还与引线框架的相应引线耦合，从而将IC连接到引线框的引线。 IC的信号焊盘连接到形成在蒸镀导电材料层内的引线框和/或信号线。 然后将IC和附接电路封装封装在塑料外壳中。

公开(公告)号：US4835120A

公开(公告)日：1989-05-30

申请号：US212882

申请日：1988-06-29

申请人： Debendra Mallik ,  Bidyut K. Bhattacharyya

发明人： Debendra Mallik ,  Bidyut K. Bhattacharyya

IPC分类号： H01L23/495 ,  H01L23/498

CPC分类号： H01L23/49527 ,  H01L23/49534 ,  H01L23/49861 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49109 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30107 ,  Y10T29/49121

摘要： A multi-layered molded plastic package for encapsulating an integrated circuit is described. The package includes a carrier having a double-layered metal plate which are separated by an adhesive coated insulation tape. A second insulating tape layer is used to bond externally extending leads onto one of the metal plates. Power and ground connections from the terminal of the integrated circuit are made to each of the plates, respectively, as are the power and ground lead connections to the two plates. The power and ground planes remove the requirement for direct physical connection between the power and ground terminals of the integrated circuit and their respective leads.

摘要翻译： 描述了用于封装集成电路的多层模制塑料封装。 该包装包括具有双层金属板的载体，其被粘合剂涂覆的绝缘带分隔开。 使用第二绝缘带层将外部延伸引线接合到其中一个金属板上。 电源和接地连接从集成电路的端子分别制成每个板，电源和接地引线连接到两个板。 电源和接地层消除了集成电路的电源和接地端子及其相应引线之间直接物理连接的要求。