COPPER INTERCONNECT STRUCTURE AND ITS FORMATION
    74.
    发明申请
    COPPER INTERCONNECT STRUCTURE AND ITS FORMATION 有权
    铜连接结构及其形成

    公开(公告)号:US20130307150A1

    公开(公告)日:2013-11-21

    申请号:US13475526

    申请日:2012-05-18

    IPC分类号: H01L23/52 H01L21/425

    摘要: A structure with improved electromigration resistance and methods for making the same. A structure having improved electromigration resistance includes a bulk interconnect having a dual layer cap and a dielectric capping layer. The dual layer cap includes a bottom metallic portion and a top metal oxide portion. Preferably the metal oxide portion is MnO or MnSiO and the metallic portion is Mn or CuMn. The structure is created by doping the interconnect with an impurity (Mn in the preferred embodiment), and then creating lattice defects at a top portion of the interconnect. The defects drive increased impurity migration to the top surface of the interconnect. When the dielectric capping layer is formed, a portion reacts with the segregated impurities, thus forming the dual layer cap on the interconnect. Lattice defects at the Cu surface can be created by plasma treatment, ion implantation, a compressive film, or other means.

    摘要翻译: 具有改进的电迁移阻力的结构及其制造方法。 具有改进的电迁移电阻的结构包括具有双层盖和介电覆盖层的体互连。 双层帽包括底部金属部分和顶部金属氧化物部分。 优选地,金属氧化物部分是MnO或MnSiO,金属部分是Mn或CuMn。 通过用杂质(在优选实施例中为Mn)掺杂互连,然后在互连的顶部处产生晶格缺陷来产生该结构。 这些缺陷驱使增加的杂质向互连顶表面迁移。 当形成电介质盖层时,一部分与分离的杂质反应,从而在互连上形成双层盖。 Cu表面的晶格缺陷可以通过等离子体处理,离子注入,压缩薄膜或其他方式产生。

    Integrated circuit chip stack employing carbon nanotube interconnects
    75.
    发明授权
    Integrated circuit chip stack employing carbon nanotube interconnects 失效
    采用碳纳米管互连的集成电路芯片堆叠

    公开(公告)号:US08586468B2

    公开(公告)日:2013-11-19

    申请号:US11210586

    申请日:2005-08-24

    IPC分类号: H01L21/28

    摘要: An arrangement of semiconductor chips is provided. The arrangement includes a plurality of stacked semiconductor chips each including an integrated circuit. At least one via is formed through the thickness of at least one of the semiconductor chips. A carbon nanotube conductor is formed in the via. The conductor has first and second opposite ends. The first end of the conductor is selectively interconnected with the integrated circuit of its semiconductor chip and the second end of the conductor is selectively interconnected with the integrated circuit of another of the semiconductor chips.

    摘要翻译: 提供了半导体芯片的布置。 该装置包括多个堆叠的半导体芯片,每个堆叠的半导体芯片均包括集成电路。 通过至少一个半导体芯片的厚度形成至少一个通孔。 在通孔中形成碳纳米管导体。 导体具有第一和第二相对端。 导体的第一端与其半导体芯片的集成电路选择性地互连,并且导体的第二端选择性地与另一个半导体芯片的集成电路互连。

    Copper interconnect formation
    76.
    发明授权
    Copper interconnect formation 失效
    铜互连形成

    公开(公告)号:US08435887B2

    公开(公告)日:2013-05-07

    申请号:US13151658

    申请日:2011-06-02

    IPC分类号: H01L21/288

    摘要: Disclosed is a method which includes forming a copper interconnect within a trench or via in a substrate. Forming the copper interconnect includes forming a ruthenium-containing seed layer on a wall of the trench or via; forming a cobalt sacrificial layer on the ruthenium-containing layer before the ruthenium-containing seed layer being exposed to an environment that is oxidizing with respect to the seed layer; and contacting the cobalt sacrificial layer with a copper plating solution, the copper plating solution dissolving the cobalt sacrificial layer and plating out copper on the unoxidized ruthenium-containing seed layer. Alternatively, the ruthenium-containing seed layer may be replaced with platinum, tungsten nitride, titanium nitride or titanium or iridium. Further alternatively, the cobalt sacrificial layer may be replaced by tin, cadmium, copper or manganese.

    摘要翻译: 公开了一种方法,其包括在衬底中的沟槽或通孔内形成铜互连。 形成铜互连包括在沟槽或通孔的壁上形成含钌种子层; 在含钌种子层暴露于相对于种子层氧化的环境之前,在含钌层上形成钴牺牲层; 并且将钴牺牲层与铜电镀溶液接触,所述铜电镀溶液溶解钴牺牲层并在未氧化的含钌种子层上电镀铜。 或者,可以用铂,氮化钨,氮化钛或钛或铱代替含钌种子层。 此外,钴牺牲层可以被锡,镉,铜或锰替代。