公开(公告)号：US11682636B2

公开(公告)日：2023-06-20

申请号：US17215297

申请日：2021-03-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Han Wang ,  Yu-Hsiang Hu ,  Hung-Jui Kuo ,  Chen-Hua Yu

IPC: H01L23/58 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L23/485 ,  H01L23/00 ,  H01L21/683 ,  H01L25/10 ,  H01L25/00

CPC classification number: H01L23/585 ,  H01L21/4857 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/485 ,  H01L24/19 ,  H01L24/20 ,  H01L21/561 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2221/68372 ,  H01L2221/68381 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1082 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/15311

Abstract: A method includes encapsulating a package component in an encapsulating material, with the encapsulating material including a portion directly over the package component. The portion of the encapsulating material is patterned to form an opening revealing a conductive feature in the package component. A redistribution line extends into the opening to contact the conductive feature. An electrical connector is formed over and electrically coupling to the conductive feature.

公开(公告)号：US20230187406A1

公开(公告)日：2023-06-15

申请号：US17651335

申请日：2022-02-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Shih-Chang Ku ,  Chien-Yuan Huang ,  Chuei-Tang Wang ,  Sey-Ping Sun

IPC: H01L23/00 ,  H01L25/065

CPC classification number: H01L24/80 ,  H01L24/08 ,  H01L24/09 ,  H01L24/03 ,  H01L25/0657 ,  H01L24/05 ,  H01L24/06 ,  H01L2224/80896 ,  H01L2224/80895 ,  H01L2225/06527 ,  H01L2225/06548 ,  H01L2224/039 ,  H01L2224/05541 ,  H01L2224/05573 ,  H01L2224/0603 ,  H01L2224/0801 ,  H01L2224/08147 ,  H01L2224/0903

Abstract: A method includes forming a first dielectric layer on a first wafer, and forming a first bond pad penetrating through the first dielectric layer. The first wafer includes a first semiconductor substrate, and the first bond pad is in contact with a first surface of the first semiconductor substrate. The method further includes forming a second dielectric layer on a second wafer and forming a second bond pad extending into the second dielectric layer. The second wafer includes a second semiconductor substrate. The first wafer is sawed into a plurality of dies, with the first bond pad being in a first die in the plurality of dies. The first bond pad is bonded to the second bond pad.

公开(公告)号：US11676906B2

公开(公告)日：2023-06-13

申请号：US16892271

申请日：2020-06-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chuei-Tang Wang ,  Chen-Hua Yu

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L25/00

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/19 ,  H01L24/20 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L2221/68372 ,  H01L2224/18 ,  H01L2224/214 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/83191 ,  H01L2225/0651 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2225/06582 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2224/73265 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2924/15311 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2224/2919 ,  H01L2924/0665 ,  H01L2924/00014

Abstract: A chip package includes a redistribution layer, at least one first semiconductor chip, an integrated fan-out package, and an insulating encapsulation. The at least one first semiconductor chip and the integrated fan-out package are electrically connected to the redistribution layer, wherein the at least one first semiconductor chip and the integrated fan-out package are located on a surface of the redistribution layer and electrically communicated to each other through the redistribution layer, and wherein the integrated fan-out package includes at least one second semiconductor chip. The insulating encapsulation encapsulates the at least one first semiconductor chip and the integrated fan-out package.

公开(公告)号：US11652086B2

公开(公告)日：2023-05-16

申请号：US17087106

申请日：2020-11-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Hsun Lee ,  Tsung-Ding Wang ,  Mirng-Ji Lii ,  Chen-Hua Yu

IPC: H01L23/48 ,  H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L23/367 ,  H01L23/373 ,  H01L23/498 ,  H01L21/78 ,  H01L25/18 ,  H01L25/00 ,  H01L23/31

CPC classification number: H01L25/0657 ,  H01L21/561 ,  H01L21/563 ,  H01L21/78 ,  H01L23/3675 ,  H01L23/3736 ,  H01L23/49827 ,  H01L24/00 ,  H01L24/97 ,  H01L25/18 ,  H01L25/50 ,  H01L23/3128 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06568 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/0002 ,  H01L2924/00 ,  H01L2224/73204 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2924/00

Abstract: A method includes bonding a first plurality of device dies onto a wafer, wherein the wafer includes a second plurality of device dies, with each of the first plurality of device dies bonded to one of the second plurality of device dies. The wafer is then sawed to form a die stack, wherein the die stack includes a first device die from the first plurality of device dies and a second device die from the second plurality of device dies. The method further includes bonding the die stack over a package substrate.

公开(公告)号：US20230114652A1

公开(公告)日：2023-04-13

申请号：US18064713

申请日：2022-12-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Kuo-Chung Yee ,  Hao-Yi Tsai ,  Tin-Hao Kuo

IPC: H01L25/065 ,  H01L21/768 ,  H01L25/00 ,  H01L21/56 ,  H01L21/3105 ,  H01L23/48 ,  H01L23/528 ,  H01L23/00 ,  H01L23/367 ,  H01L23/31 ,  H01L23/538

Abstract: A method includes forming a first through-via from a first conductive pad of a first device die, and forming a second through-via from a second conductive pad of a second device die. The first and second conductive pads are at top surfaces of the first and the second device dies, respectively. The first and the second conductive pads may be used as seed layers. The second device die is adhered to the top surface of the first device die. The method further includes encapsulating the first and the second device dies and the first and the second through-vias in an encapsulating material, with the first and the second device dies and the first and the second through-vias encapsulated in a same encapsulating process. The encapsulating material is planarized to reveal the first and the second through-vias. Redistribution lines are formed to electrically couple to the first and the second through-vias.

公开(公告)号：US20230109686A1

公开(公告)日：2023-04-13

申请号：US18064667

申请日：2022-12-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  An-Jhih Su ,  Wei-Yu Chen

IPC: H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/522 ,  H01L23/528 ,  H01L23/538 ,  G02B6/30 ,  G02B6/122 ,  G02B6/136

Abstract: A method includes placing an electronic die and a photonic die over a carrier, with a back surface of the electronic die and a front surface of the photonic die facing the carrier. The method further includes encapsulating the electronic die and the photonic die in an encapsulant, planarizing the encapsulant until an electrical connector of the electronic die and a conductive feature of the photonic die are revealed, and forming redistribution lines over the encapsulant. The redistribution lines electrically connect the electronic die to the photonic die. An optical coupler is attached to the photonic die. An optical fiber attached to the optical coupler is configured to optically couple to the photonic die.

公开(公告)号：US11625940B2

公开(公告)日：2023-04-11

申请号：US17106644

申请日：2020-11-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Yu-Feng Chen ,  Chih-Hua Chen ,  Hao-Yi Tsai ,  Chung-Shi Liu

IPC: G06K9/00 ,  H01L21/56 ,  H01L21/768 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01L23/00 ,  H01L25/16 ,  G06V40/13

Abstract: A fingerprint sensor package and method are provided. The fingerprint sensor package comprises a fingerprint sensor along with a fingerprint sensor surface material and electrical connections from a first side of the fingerprint sensor to a second side of the fingerprint sensor. A high voltage chip is connected to the fingerprint sensor and then the fingerprint sensor package with the high voltage chip are connected to a substrate, wherein the substrate has an opening to accommodate the presence of the high voltage chip.

公开(公告)号：US11614592B2

公开(公告)日：2023-03-28

申请号：US16930702

申请日：2020-07-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Ming Weng ,  Chen-Hua Yu ,  Chung-Shi Liu ,  Hao-Yi Tsai ,  Cheng-Chieh Hsieh ,  Hung-Yi Kuo ,  Chih-Hsuan Tai ,  Hua-Kuei Lin ,  Tsung-Yuan Yu ,  Min-Hsiang Hsu

IPC: G02B6/42 ,  H01L25/16 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48

Abstract: Photonic devices and methods of manufacture are provided. In embodiments a fill material and/or a secondary waveguide are utilized in order to protect other internal structures such as grating couplers from the rigors of subsequent processing steps. Through the use of these structures at the appropriate times during the manufacturing process, damage and debris that would otherwise interfere with the manufacturing process of the device or operation of the device can be avoided.

公开(公告)号：US20230069031A1

公开(公告)日：2023-03-02

申请号：US17412966

申请日：2021-08-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jiun Yi Wu ,  Chen-Hua Yu ,  Chung-Shi Liu

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/498 ,  H01L25/00 ,  H01L21/48

Abstract: A semiconductor structure includes a first redistribution structure, a first local interconnect component disposed on the first redistribution structure, and a first interconnect structure over a second side of the first local interconnect component. The first local interconnect component includes a first plurality of redistribution layers. The first plurality of redistribution layers includes a first plurality of conductive features on a first side of the first local interconnect component. Each of the first plurality of conductive features are coupled to respective conductive features of the first redistribution structure. The first interconnect structure includes a second plurality of conductive features and a third plurality of conductive features. The second plurality of conductive features are electrically coupled to the third plurality of conductive features through the first local interconnect component.

公开(公告)号：US11594498B2

公开(公告)日：2023-02-28

申请号：US16931992

申请日：2020-07-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jiun Yi Wu ,  Chen-Hua Yu ,  Chung-Shi Liu

IPC: H01L23/538 ,  H01L21/48 ,  H01L25/00 ,  H01L25/065 ,  H01L23/00

Abstract: In an embodiment, a structure includes a core substrate, a redistribution structure coupled, the redistribution structure including a plurality of redistribution layers, the plurality of redistribution layers comprising a dielectric layer and a metallization layer, a first local interconnect component embedded in a first redistribution layer of the plurality of redistribution layers, the first local interconnect component comprising conductive connectors, the conductive connectors being bonded to a metallization pattern of the first redistribution layer, the dielectric layer of the first redistribution layer encapsulating the first local interconnect component, a first integrated circuit die coupled to the redistribution structure, a second integrated circuit die coupled to the redistribution structure, an interconnect structure of the first local interconnect component electrically coupling the first integrated circuit die to the second integrated circuit die, and a set of conductive connectors coupled to a second side of the core substrate.