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公开(公告)号：US20090033308A1
公开(公告)日：2009-02-05
申请号：US12245360
申请日：2008-10-03
IPC分类号： G05F5/00
摘要： A system may include acquisition of a supply voltage information representing past supply voltages supplied to an electrical component, acquisition of a temperature information representing past temperatures of the electrical component, and control of a performance characteristic of the electrical component based on the supply voltage information and the temperature information. Some embodiments may further include determination of a reliability margin based on the supply voltage information, the temperature information, and on a reliability specification of the electrical component, and change of the performance characteristic based on the reliability margin.
摘要翻译： 系统可以包括获取表示提供给电气部件的过去电源电压的电源电压信息，基于电源电压信息获取表示电气部件的过去温度的温度信息和电气部件的性能特性的控制，以及 温度信息。 一些实施例还可以包括基于电源电压信息，温度信息以及电气部件的可靠性规格以及基于可靠性裕度的性能特性的改变来确定可靠性裕度。
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公开(公告)号：US07288752B2
公开(公告)日：2007-10-30
申请号：US10620829
申请日：2003-07-16
申请人： Ali Keshavarzi , Jaume A. Segura , Vivek K. De
发明人： Ali Keshavarzi , Jaume A. Segura , Vivek K. De
CPC分类号： G01T1/026 , H01L27/144
摘要： A radiation measuring technique includes adjusting a threshold level of a radiation sensor in a radiation-measuring circuit and obtaining an output signal based on radiation dose sensed by the radiation sensor.
摘要翻译： 辐射测量技术包括调整辐射测量电路中的辐射传感器的阈值水平，并且基于由辐射传感器感测的辐射剂量获得输出信号。
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公开(公告)号：US07282966B2
公开(公告)日：2007-10-16
申请号：US10953199
申请日：2004-09-28
IPC分类号： H03K17/00
CPC分类号： G06F1/324 , G06F1/06 , G06F1/206 , G06F1/3203 , Y02D10/126
摘要： Apparatus and systems, as well as methods and articles, may operate to select a microprocessor clock frequency responsive to a desired voltage and/or a desired temperature of operation.
摘要翻译： 装置和系统以及方法和物品可以操作以响应于期望电压和/或期望的操作温度来选择微处理器时钟频率。
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公开(公告)号：US07109776B2
公开(公告)日：2006-09-19
申请号：US10947869
申请日：2004-09-23
申请人： James W. Tschanz , Dinesh Somasekhar , Vivek K. De
发明人： James W. Tschanz , Dinesh Somasekhar , Vivek K. De
IPC分类号： H03K3/013
CPC分类号： G06F1/10
摘要： Some embodiments provide reception of a clock signal, reception of a gating signal, and output of a gated clock signal to a dual edge-triggered-clocked circuit. The gated clock signal is based on the clock signal and on the gating signal.
摘要翻译： 一些实施例提供时钟信号的接收，门控信号的接收以及门控时钟信号输出到双边沿触发时钟电路。 门控时钟信号基于时钟信号和门控信号。
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公开(公告)号：US07098766B2
公开(公告)日：2006-08-29
申请号：US10760591
申请日：2004-01-21
申请人： Donald S. Gardner , Peter Hazucha , Gerhard Schrom , Tanay Karnik , Vivek K. De
发明人： Donald S. Gardner , Peter Hazucha , Gerhard Schrom , Tanay Karnik , Vivek K. De
IPC分类号： H01F5/00
CPC分类号： H01F17/0006 , H01F10/132 , H01F10/187 , H01F10/265 , H01F2017/0053
摘要： A transformer is provided that includes a plurality of metal lines and a magnetic material provided about the plurality of metal lines. The magnetic material may include a structure to reduce Eddy currents flowing in the magnetic material. This structure may be a plurality of slots extending perpendicular to the metal lines. This structure may also be a laminated structure.
摘要翻译： 提供一种变压器，其包括多个金属线和围绕多条金属线设置的磁性材料。 磁性材料可以包括减少在磁性材料中流动的涡流的结构。 该结构可以是垂直于金属线延伸的多个槽。 该结构也可以是层叠结构。
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76.发明授权公开(公告)号：US07075180B2
公开(公告)日：2006-07-11
申请号：US10747805
申请日：2003-12-29
CPC分类号： H01L23/367 , H01L23/50 , H01L24/31 , H01L24/75 , H01L24/81 , H01L24/83 , H01L2224/16225 , H01L2224/73253 , H01L2224/75 , H01L2224/81801 , H01L2224/83801 , H01L2924/01005 , H01L2924/01015 , H01L2924/01023 , H01L2924/01033 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2924/15174 , H01L2924/15311 , H01L2924/16152
摘要： In some embodiments, a method includes providing an integrated circuit (IC) die in a package. The IC die may have a metal layer on a back surface of the IC die. The method may also include applying a bias signal to the IC die via the metal layer.
摘要翻译： 在一些实施例中，一种方法包括在封装中提供集成电路（IC）裸片。 IC芯片可以在IC芯片的背面上具有金属层。 该方法还可以包括经由金属层向IC管芯施加偏置信号。
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77.发明授权IC design process including automated removal of body contacts from MOSFET devices 有权IC设计过程包括从MOSFET器件自动移除主体触点公开(公告)号：US07051295B2
公开(公告)日：2006-05-23
申请号：US10746759
申请日：2003-12-23
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： An apparatus for and method of modifying an IC design layout of an integrated circuit, comprising: accessing an initial IC design layout, with the initial layout including a plurality of MOSFET devices having a common substrate; and removing a plurality of body contacts of the MOSFET devices to create a first modified IC design layout.
摘要翻译： 一种用于修改集成电路的IC设计布局的装置和方法，包括：访问初始IC设计布局，初始布局包括具有公共衬底的多个MOSFET器件; 以及去除所述MOSFET器件的多个体接触以产生第一修改的IC设计布局。
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公开(公告)号：US07015720B2
公开(公告)日：2006-03-21
申请号：US10749928
申请日：2003-12-29
申请人： Gerhard Schrom , Peter Hazucha , Jae-Hong Hahn , Vivek K. De
发明人： Gerhard Schrom , Peter Hazucha , Jae-Hong Hahn , Vivek K. De
IPC分类号： H03K19/0175
CPC分类号： H03K17/691 , H03K19/0013
摘要： A circuit includes a first driver, a second driver, and a transformer coupled to the first and second driver. In operation, the first driver receives a first signal from a first input port, the second driver receives a time-delayed version of the first signal from a second input port, and the transformer provides provide an output signal to an output port. A method includes receiving a first input signal, receiving a second input signal, and then processing the first input signal and the second input signal. The second input signal is a time-delayed version of the first input signal and the processing of the first input signal and the second input signal generates a half-raised cosine signal.
摘要翻译： 电路包括第一驱动器，第二驱动器和耦合到第一和第二驱动器的变压器。 在操作中，第一驱动器从第一输入端口接收第一信号，第二驱动器从第二输入端口接收第一信号的时间延迟版本，并且变压器向输出端口提供输出信号。 一种方法包括接收第一输入信号，接收第二输入信号，然后处理第一输入信号和第二输入信号。 第二输入信号是第一输入信号的时间延迟版本，第一输入信号和第二输入信号的处理产生半升余弦信号。
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公开(公告)号：US06992603B2
公开(公告)日：2006-01-31
申请号：US10813084
申请日：2004-03-31
申请人： Maged M. Ghoneima , Peter Caputa , Muhammad M. Khellah , Ram Krishnamurthy , James W. Tschanz , Yiben Ye , Vivek K. De , Yehea I Ismail
发明人： Maged M. Ghoneima , Peter Caputa , Muhammad M. Khellah , Ram Krishnamurthy , James W. Tschanz , Yiben Ye , Vivek K. De , Yehea I Ismail
IPC分类号： H03M7/00
CPC分类号： G06F13/4072 , Y02D10/14 , Y02D10/151
摘要： An interconnect architecture is provided to reduce power consumption. A first driver may drive signals on a first interconnect and a second driver may drive signals on a second interconnect. The first driver may be powered by a first voltage and the second driver may be powered by a second voltage different than the first voltage.
摘要翻译： 提供互连架构以降低功耗。 第一驱动器可以在第一互连上驱动信号，并且第二驱动器可以在第二互连上驱动信号。 第一驱动器可以由第一电压供电，并且第二驱动器可以由不同于第一电压的第二电压供电。
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公开(公告)号：US06970018B2
公开(公告)日：2005-11-29
申请号：US10873243
申请日：2004-06-23
申请人： Dejan Markovic , James W. Tschanz , Vivek K. De
发明人： Dejan Markovic , James W. Tschanz , Vivek K. De
IPC分类号： H03K3/012 , H03K3/037 , H03K3/356 , H03K19/094
CPC分类号： H03K3/356113 , H03K3/012 , H03K3/037 , H03K3/356156
摘要： A cycle latch includes a control circuit which increases the pull-up rate of a storage node by conditionally discharging the feedback node in a cross-coupled inverter keeper structure. The cycle latch includes an NMOS transistor switch for transferring an input value to the storage node, and two more NMOS transistors connected in series for performing the function of the control circuit. By connecting the storage node to a pre-discharged feedback node and then driving the latch with a low-swing clock, improved performance in terms of delay times, energy consumption, and robustness is achieved.
摘要翻译： 循环锁存器包括控制电路，其通过在交叉耦合的逆变器保持器结构中有条件地排放反馈节点来增加存储节点的上拉率。 周期锁存器包括用于将输入值传送到存储节点的NMOS晶体管开关和串联连接的两个NMOS晶体管，用于执行控制电路的功能。 通过将存储节点连接到预放电反馈节点，然后用低摆频时钟驱动锁存器，实现延迟时间，能量消耗和鲁棒性方面的改进的性能。
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