公开(公告)号：US11894093B2

公开(公告)日：2024-02-06

申请号：US17568649

申请日：2022-01-04

Applicant: Rambus Inc.

Inventor： Thomas Vogelsang

IPC: G11C5/06 ,  H01L23/48 ,  H01L25/065 ,  H10B12/00 ,  G11C5/02

CPC classification number: G11C5/063 ,  G11C5/025 ,  H01L23/481 ,  H01L25/0657 ,  H10B12/50 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06596 ,  H01L2924/0002 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A memory device includes a first dynamic random access memory (DRAM) integrated circuit (IC) chip including first memory core circuitry, and first input/output (I/O) circuitry. A second DRAM IC chip is stacked vertically with the first DRAM IC chip. The second DRAM IC chip includes second memory core circuitry, and second I/O circuitry. Solely one of the first DRAM IC chip or the second DRAM IC chip includes a conductive path that electrically couples at least one of the first memory core circuitry or the second memory core circuitry to solely one of the first I/O circuitry or the second I/O circuitry, respectively.

公开(公告)号：US20240037055A1

公开(公告)日：2024-02-01

申请号：US18230375

申请日：2023-08-04

Applicant: Rambus Inc.

Inventor： Steven C. WOO

IPC: G06F13/40 ,  H01L25/065 ,  G06N3/045

CPC classification number: G06F13/4027 ,  H01L25/0652 ,  G06N3/045

Abstract: Multiple device stacks are interconnected in a ring topology. The inter-device stack communication may utilize a handshake protocol. This ring topology may include the host so that the host may initialize and load the device stacks with data and/or commands (e.g., software, algorithms, etc.). The inter-device stack interconnections may also be configured to include/remove the host and/or to implement varying numbers of separate ring topologies. By configuring the system with more than one ring topology, and assigning different problems to different rings, multiple, possibly unrelated, machine learning tasks may be performed in parallel by the device stack system.

公开(公告)号：US11876652B2

公开(公告)日：2024-01-16

申请号：US17400823

申请日：2021-08-12

Applicant: Rambus Inc.

Inventor： Masum Hossain ,  Maruf H. Mohammad

IPC: H04L25/49 ,  H04L25/03

CPC classification number: H04L25/4917 ,  H04L25/03019 ,  H04L25/03178

Abstract: Methods and apparatuses for direct sequence detection can receive an input signal over a communication channel. Next, the input signal can be sampled based on a clock signal to obtain a sampled voltage. A set of reference voltages can be generated based on a main cursor, a set of pre-cursors, and a set of post-cursors associated with the communication channel. Each generated reference voltage in the set of reference voltages can correspond to a particular sequence of symbols. A sequence corresponding to the sampled voltage can be selected based on comparing the sampled voltage with the set of reference voltages.

公开(公告)号：US20240013819A1

公开(公告)日：2024-01-11

申请号：US18348716

申请日：2023-07-07

Applicant: Rambus Inc.

Inventor： Taeksang Song ,  Steven Woo ,  Craig Hampel ,  John Eric Linstadt

IPC: G11C7/10

CPC classification number: G11C7/1084 ,  G11C7/1006

Abstract: An apparatus and method for flexible metadata allocation and caching. In one embodiment of the method first and second requests are received from first and second applications, respectively, wherein the requests specify a reading of first and second data, respectively, from one or more memory devices. The circuit reads the first and second data in response to receiving the first and second requests. Receiving first and second metadata from the one or more memory devices in response to receiving the first and second requests. The first and second metadata correspond to the first and second data, respectively. The first and second data are equal in size, and the first and second metadata are unequal in size.

公开(公告)号：US20240012710A1

公开(公告)日：2024-01-11

申请号：US18213828

申请日：2023-06-24

Applicant: Rambus Inc.

Inventor： Evan Lawrence ERICKSON ,  John Eric LINSTADT

IPC: G06F11/10

CPC classification number: G06F11/10

Abstract: When writing a block (e.g., cache line) of data to a memory, error detection and correction (EDC) information (check) symbols are calculated. The block of data, a first portion of the check symbols, and metadata are all written concurrently at a first address. The remaining portion of the check symbols are written at a second, different from the first, address. When reading the block of data, a first read command accesses the block of data, the first portion of the check symbols, and the metadata from the first address. Only the first portion of the check symbols is used to determine a first number of errors (if any) in the accessed data. If the first number of errors meets a threshold number of errors, a second read command is issued to access the second portion of the check symbols.

公开(公告)号：US20230420010A1

公开(公告)日：2023-12-28

申请号：US18340803

申请日：2023-06-23

Applicant: Rambus Inc.

Inventor： Richard E. Perego ,  Frederick A. Ware

IPC: G11C7/10 ,  G06F13/16 ,  G11C5/06

CPC classification number: G11C7/1072 ,  G06F13/1678 ,  G06F13/1684 ,  G06F13/1694 ,  G11C5/06 ,  G11C7/1045 ,  G11C7/1075

Abstract: A memory system includes a memory controller with a plurality N of memory-controller blocks, each of which conveys independent transaction requests over external request ports. The request ports are coupled, via point-to-point connections, to from one to N memory devices, each of which includes N independently addressable memory blocks. All of the external request ports are connected to respective external request ports on the memory device or devices used in a given configuration. The number of request ports per memory device and the data width of each memory device changes with the number of memory devices such that the ratio of the request-access granularity to the data granularity remains constant irrespective of the number of memory devices.

公开(公告)号：US11854658B2

公开(公告)日：2023-12-26

申请号：US17696818

申请日：2022-03-16

Applicant: Rambus Inc.

Inventor： Christopher Haywood ,  David Wang

IPC: G11C7/10 ,  G06F11/10 ,  G06F11/07 ,  G11C29/52 ,  G11C29/04 ,  G11C5/04

CPC classification number: G11C7/1072 ,  G06F11/073 ,  G06F11/0778 ,  G06F11/0787 ,  G06F11/1044 ,  G06F11/1048 ,  G06F11/1068 ,  G11C7/1006 ,  G06F11/1008 ,  G11C5/04 ,  G11C29/52 ,  G11C2029/0411

Abstract: A method for operating a DRAM device. The method includes receiving in a memory buffer in a first memory module hosted by a computing system, a request for data stored in RAM of the first memory module from a host controller of the computing system. The method includes receiving with the memory buffer, the data associated with a RAM, in response to the request and formatting with the memory buffer, the data into a scrambled data in response to a pseudo-random process. The method includes initiating with the memory buffer, transfer of the scrambled data into an interface device.

公开(公告)号：US20230412213A1

公开(公告)日：2023-12-21

申请号：US18195524

申请日：2023-05-10

Applicant: Rambus Inc.

Inventor： John W. POULTON ,  Frederick A. WARE ,  Carl W. WERNER

IPC: H04B3/56 ,  H04L25/02 ,  G06F13/40 ,  H03F3/24 ,  H04B3/54

CPC classification number: H04B3/56 ,  H04L25/0272 ,  H04B10/50 ,  H03F3/24 ,  H04B3/54 ,  G06F13/4072

Abstract: A single-ended data transmission system transmits a signal having a signal voltage that is referenced to a power supply voltage and that swings above and below the power supply voltage. The power supply voltage is coupled to a power supply rail that also serves as a signal return path. The signal voltage is derived from two signal supply voltages generated by a pair of charge pumps that draw substantially same amount of current from a power supply.

公开(公告)号：US11843372B2

公开(公告)日：2023-12-12

申请号：US17235283

申请日：2021-04-20

Applicant: Rambus Inc.

Inventor： Huy Nguyen

IPC: H03K19/00 ,  H04B1/04 ,  H04L25/02

CPC classification number: H03K19/0005 ,  H04B1/0458 ,  H04L25/0278 ,  H04L25/0298

Abstract: Described are integrated-circuit die with differential receivers, the inputs of which are coupled to external signal pads. Termination legs coupled to the signal pads support multiple termination topologies. These termination legs can support adjustable impedances, capacitances, or both, which may be controlled using an integrated memory.

公开(公告)号：US11842761B2

公开(公告)日：2023-12-12

申请号：US17390370

申请日：2021-07-30

Applicant: Rambus Inc.

Inventor： Thomas Vogelsang ,  John Eric Linstadt ,  Liji Gopalakrishnan

IPC: G06F12/00 ,  G11C11/408 ,  G11C11/4094 ,  G11C11/4091 ,  G06F13/42

CPC classification number: G11C11/4085 ,  G06F13/4282 ,  G11C11/4091 ,  G11C11/4094

Abstract: A dynamic random access memory (DRAM) component (e.g., module or integrated circuit) can be configured to have multiple rows in the same bank open concurrently. The controller of the component divides the address space of the banks into segments based on row address ranges. These row address ranges do not necessarily correspond to row address ranges of the bank's subarrays (a.k.a. memory array tiles—MATs). When a command is sent to open a row, the controller marks a plurality of the segments as blocked. The controller thereby tracks address ranges in a bank where it will not open a second row unless and until the first row is closed. The memory component may store information about which, and how many, segments should be blocked in response to opening a row. This information may be read by the controller during initialization.