公开(公告)号：US09681077B2

公开(公告)日：2017-06-13

申请号：US13546882

申请日：2012-07-11

Applicant: Cedric Tubert ,  Francois Roy ,  Pascal Mellot

Inventor： Cedric Tubert ,  Francois Roy ,  Pascal Mellot

IPC: H01L29/06 ,  H04N5/372

CPC classification number: H04N5/372 ,  H01L29/06 ,  H01L29/0603

Abstract: A device for transferring charges photogenerated in a portion of a semiconductor layer delimited by at least two parallel trenches, each trench including, lengthwise, at least a first and a second conductive regions insulated from each other and from the semiconductor layer, including the repeating of a first step of biasing of the first conductive regions to a first voltage to form a volume accumulation of holes in the area of this portion located between the first regions, while the second conductive regions are biased to a second voltage greater than the first voltage, and of a second step of biasing of the first regions to the second voltage and of the second regions to the first voltage.

公开(公告)号：US09673088B2

公开(公告)日：2017-06-06

申请号：US14970792

申请日：2015-12-16

Applicant: STMicroelectronics SA

Inventor： Sylvain Joblot ,  Pierre Bar

IPC: H01L21/768 ,  G02B6/12 ,  H01P11/00 ,  H01L21/762 ,  H01L21/48

CPC classification number: H01L21/76831 ,  G02B6/12 ,  H01L21/4846 ,  H01L21/76224 ,  H01L21/76898 ,  H01L23/66 ,  H01P11/003

Abstract: An integrated circuit includes a silicon-on-insulator wafer and interconnect layer providing a support for a coplanar waveguide formed above a top side of the support. A through-silicon via is formed from a back side of the support and passing through the silicon-on-insulator wafer to reach the interconnect layer. A trench is formed from the back side of the support underneath the coplanar waveguide. The trench extends over at least an entire length of the coplanar waveguide. The trench passes through the silicon-on-insulator wafer to reach the interconnect layer and may have a substantially same depth as the through-silicon via.

公开(公告)号：US09666577B2

公开(公告)日：2017-05-30

申请号：US14450597

申请日：2014-08-04

Applicant: Commissariat à l'énergie atomique et aux énergies alternatives ,  STMicroelectronics SA ,  Centre National de la Recherche Scientifique

Inventor： Yohann Solaro ,  Sorin Cristoloveanu ,  Claire Fenouillet-Beranger ,  Pascal Fonteneau

IPC: H01L27/02 ,  H01L27/12 ,  H01L29/66 ,  H01L29/747 ,  H01L29/78 ,  H01L29/423 ,  H01L29/74 ,  H01L29/749 ,  H01L29/10

CPC classification number: H01L27/0262 ,  H01L27/1203 ,  H01L29/1012 ,  H01L29/42308 ,  H01L29/66477 ,  H01L29/7436 ,  H01L29/747 ,  H01L29/749 ,  H01L29/78 ,  H01L29/7833

Abstract: The invention relates to an IC with an electrostatic discharge protection device. There is a buried insulant layer 50 nm or less in thickness and first and second bipolar transistors on the insulant layer, one being an npn transistor and the other a pnp transistor. The base of the first transistor is merged with the collector of the second transistor and the base of the second transistor is merged with the collector of the first transistor. The first and second bipolar transistors are configured to selectively conduct a discharge current between two electrodes of the protection device. There is a first semiconductor ground plane under the insulant layer, being electrically biased, extending until it is plumb with the base of the first bipolar transistor, exhibiting a first type of doping identical to that of the base of the first bipolar transistor with a doping density at least ten times greater.

公开(公告)号：US09640704B2

公开(公告)日：2017-05-02

申请号：US15163550

申请日：2016-05-24

Applicant: Commissariat à l'Énergie Atomique et aux Énergies Alternatives ,  STMicroelectronics SA

Inventor： Laurent Frey ,  Michel Marty

IPC: H01L29/49 ,  H01L31/113 ,  H01L31/0232 ,  H01L31/107 ,  H01L27/146

CPC classification number: H01L31/1133 ,  H01L27/14603 ,  H01L27/14643 ,  H01L31/02327 ,  H01L31/107

Abstract: A photodetector including a photoelectric conversion structure made of a semiconductor material and, on a light-receiving surface of the conversion structure, a stack of first and second diffractive elements, the second element being above the first element, wherein: the first element includes at least one pad made of a material having an optical index n1, laterally surrounded with a region made of a material having an optical index n2 different from n1; the second element includes at least one pad made of a material having an optical index n3, laterally surrounded with a region made of a material having an optical index n4 different from n3; the pads of the first and second elements are substantially vertically aligned; and optical index differences n1−n2 and n3−n4 have opposite signs.

公开(公告)号：US09564242B2

公开(公告)日：2017-02-07

申请号：US14832802

申请日：2015-08-21

Applicant: STMicroelectronics SA

Inventor： Philippe Candelier ,  Joel Damiens ,  Elise Le Roux

IPC: G11C17/16 ,  G11C17/18 ,  H01L27/12 ,  H01L27/112 ,  H01L27/10

CPC classification number: G11C17/165 ,  G11C17/18 ,  H01L27/101 ,  H01L27/11206

Abstract: A method for controlling the breakdown of an antifuse memory cell formed on a semiconductor substrate, including the steps of: applying a programming voltage; detecting a breakdown time; and interrupting the application of the programming voltage at a time following the breakdown time by a post-breakdown time.

Abstract translation: 一种用于控制形成在半导体衬底上的反熔层存储单元击穿的方法，包括以下步骤：施加编程电压; 检测故障时间; 并且在故障时间之后的故障时间之后中断施加编程电压。

公开(公告)号：US09543214B2

公开(公告)日：2017-01-10

申请号：US14526081

申请日：2014-10-28

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics, Inc.

Inventor： Denis Rideau ,  Elise Baylac ,  Emmanuel Josse ,  Pierre Morin ,  Olivier Nier

IPC: H01L21/8234 ,  H01L21/84 ,  H01L21/762 ,  H01L29/78 ,  H01L21/02 ,  H01L21/265 ,  H01L21/3115 ,  H01L21/308 ,  H01L21/3105 ,  H01L21/324 ,  H01L27/12

CPC classification number: H01L21/823481 ,  H01L21/02356 ,  H01L21/02532 ,  H01L21/265 ,  H01L21/26506 ,  H01L21/3081 ,  H01L21/3105 ,  H01L21/31155 ,  H01L21/324 ,  H01L21/76224 ,  H01L21/76237 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/1203 ,  H01L29/7831 ,  H01L29/7846 ,  H01L29/7847

Abstract: The invention concerns a method of forming a semiconductor layer having uniaxial stress including: forming, in a semiconductor structure having a stressed semiconductor layer, one or more first isolation trenches in a first direction for delimiting a first dimension of at least one transistor to be formed in said semiconductor structure; forming, in the semiconductor structure, one or more second isolation trenches in a second direction for delimiting a second dimension of the at least one transistor, the first and second isolation trenches being at least partially filled with an insulating material; and before or after the formation of the second isolation trenches, decreasing the viscosity of the insulating material in the first isolation trenches by implanting atoms of a first material into the first isolation trenches, wherein atoms of the first material are not implanted into the second isolation trenches.

Abstract translation: 本发明涉及一种形成具有单轴应力的半导体层的方法，包括：在具有应力半导体层的半导体结构中形成在第一方向上的一个或多个第一隔离沟槽，以限定待形成的至少一个晶体管的第一维度 在所述半导体结构中; 在所述半导体结构中，在第二方向上形成用于限定所述至少一个晶体管的第二尺寸的一个或多个第二隔离沟槽，所述第一和第二隔离沟槽至少部分地填充有绝缘材料; 并且在形成第二隔离沟槽之前或之后，通过将第一材料的原子注入到第一隔离沟槽中来降低第一隔离沟槽中的绝缘材料的粘度，其中第一材料的原子未被注入第二隔离层 沟渠

公开(公告)号：US20170003571A1

公开(公告)日：2017-01-05

申请号：US15068704

申请日：2016-03-14

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA

Inventor： Jean-Francois Carpentier ,  Patrick LeMaitre ,  Denis Pache

IPC: G02F1/225 ,  G02F1/025 ,  G02F1/01

CPC classification number: G02F1/2255 ,  G02F1/0123 ,  G02F1/025 ,  G02F1/2257 ,  G02F2001/212

Abstract: An integrated modulator of the Mach-Zehnder type includes two optical arms containing waveguides with PN junctions and biasing circuits for reverse biasing the PN junctions in response to a control signal. The two optical arms are situated within a semiconductor substrate of a first element that also has an interconnection region. The biasing circuits are situated, in part, within a substrate of a second element that also contains an interconnection region. The first and second elements are rigidly attached to each other via their respective interconnection regions.

Abstract translation: Mach-Zehnder型集成调制器包括两个含有PN结的波导的光学臂和用于响应控制信号反向偏置PN结的偏置电路。 两个光学臂位于也具有互连区域的第一元件的半导体衬底内。 偏置电路部分地位于也包含互连区域的第二元件的衬底内。 第一和第二元件通过其相应的互连区域彼此刚性连接。

公开(公告)号：US09530817B2

公开(公告)日：2016-12-27

申请号：US14953973

申请日：2015-11-30

Applicant: STMicroelectronics SA ,  Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Michel Marty ,  Laurent Frey

IPC: H01L29/06 ,  H01L27/14 ,  H01L31/062 ,  H01L21/00 ,  H01L27/146 ,  H01L31/0232 ,  H01L31/107 ,  H01L31/0352

CPC classification number: H01L27/14685 ,  H01L27/14621 ,  H01L27/14625 ,  H01L27/14627 ,  H01L27/1464 ,  H01L27/14643 ,  H01L31/02327 ,  H01L31/035236 ,  H01L31/107

Abstract: A back side illumination photodiode includes a light-receiving back side surface of a semiconductor material substrate. An area of the light-receiving back side surface includes a recess. The recess is filled with a material having an optical index that is lower than an optical index of the semiconductor material substrate. Both the substrate and the filling material are transparent to an operating wavelength of the photodiode. The recess may be formed to have a ring shape.

公开(公告)号：US09507181B2

公开(公告)日：2016-11-29

申请号：US15198114

申请日：2016-06-30

Applicant: STMICROELECTRONICS SA

Inventor： Jean-Robert Manouvrier

IPC: G02F1/025 ,  G02F1/225 ,  G02B6/12 ,  H04B10/54 ,  H04B10/548

CPC classification number: G02F1/025 ,  G02B6/12 ,  G02F1/2257 ,  H04B10/548

Abstract: A semiconductor electro-optical phase shifter may include an optical action zone configured to be inserted in an optical waveguide, and a bipolar transistor structure configured so that, in operation, collector current of the bipolar transistor structure crosses the optical action zone perpendicular to the axis of the optical waveguide.

Abstract translation: 半导体电光移相器可以包括被配置为插入在光波导中的光学作用区域和双极晶体管结构，其被配置为使得在操作中双极晶体管结构的集电极电流与垂直于轴线的光学作用区域相交 的光波导。

公开(公告)号：US20160322276A1

公开(公告)日：2016-11-03

申请号：US15204488

申请日：2016-07-07

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Pierre Bar ,  Alisee Taluy ,  Olga Kokshagina

IPC: H01L23/367 ,  H01L23/31 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/3675 ,  H01L21/32139 ,  H01L21/4853 ,  H01L21/4871 ,  H01L21/4882 ,  H01L21/563 ,  H01L21/565 ,  H01L21/76897 ,  H01L23/3135 ,  H01L23/3157 ,  H01L23/36 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/13147 ,  H01L2224/14131 ,  H01L2224/14519 ,  H01L2224/29013 ,  H01L2224/29082 ,  H01L2224/29111 ,  H01L2224/29147 ,  H01L2224/2919 ,  H01L2224/3015 ,  H01L2224/30519 ,  H01L2224/32225 ,  H01L2224/73103 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/83193 ,  H01L2224/83801 ,  H01L2224/9211 ,  H01L2924/12042 ,  H01L2924/18161 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2224/83

Abstract: A device includes a chip assembled on an interposer. An electrically-insulating layer coats an upper surface of the interposer around the chip. First metal lines run on the upper surface of the interposer and are arranged between conductive elements of connection to the chip. An end of each first metal line is arranged to extend beyond a projection of the chip on the interposer. A thermally-conductive via connects the end of the first metal line to a heat sink supported at an upper surface of the device.