公开(公告)号：US09767044B2

公开(公告)日：2017-09-19

申请号：US14034813

申请日：2013-09-24

Applicant: Intel Corporation

Inventor： Siddhartha Chhabra ,  Uday R. Savagaonkar ,  Michael A. Goldsmith ,  Simon P. Johnson ,  Rebekah M. Leslie-Hurd ,  Francis X. McKeen ,  Gilbert Neiger ,  Raghunandan Makaram ,  Carlos V. Rozas ,  Amy L. Santoni ,  Vincent R. Scarlata ,  Vedvyas Shanbhogue ,  Wesley H. Smith ,  Ittai Anati ,  Ilya Alexandrovich

IPC: G06F12/00 ,  G06F12/14 ,  G06F12/0808 ,  G06F12/1027 ,  G06F9/455 ,  G06F12/0897

CPC classification number: G06F12/1408 ,  G06F9/45558 ,  G06F12/0808 ,  G06F12/0897 ,  G06F12/1027 ,  G06F2009/45587 ,  G06F2212/1032 ,  G06F2212/1048 ,  G06F2212/152

Abstract: Secure memory repartitioning technologies are described. A processor includes a processor core and a memory controller coupled between the processor core and main memory. The main memory includes a memory range including a section of convertible pages that are convertible to secure pages or non-secure pages. The processor core, in response to a page conversion instruction, is to determine from the instruction a convertible page in the memory range to be converted and convert the convertible page to be at least one of a secure page or a non-secure page. The memory range may also include a hardware reserved section that is convertible in response to a section conversion instruction.

公开(公告)号：US09760489B2

公开(公告)日：2017-09-12

申请号：US15210962

申请日：2016-07-15

Applicant: International Business Machines Corporation

Inventor： David M. Daly ,  Vijayalakshmi Srinivasan

IPC: G06F12/00 ,  G06F12/0815 ,  G06F12/0817 ,  G06F12/084 ,  G06F3/06 ,  G06F12/0831

CPC classification number: G06F12/0815 ,  G06F3/06 ,  G06F12/0817 ,  G06F12/0831 ,  G06F12/084 ,  G06F2212/1008 ,  G06F2212/1016 ,  G06F2212/1021 ,  G06F2212/1048 ,  G06F2212/151 ,  G06F2212/251 ,  G06F2212/283 ,  G06F2212/608 ,  G06F2212/621

Abstract: A mechanism is provided for memory coherence in a multiple processor system. Responsive to a memory operation from a processing core of the multiple processor system resulting in a cache miss, the mechanism checks a private region table associated with the processing core. The memory operation attempts to access a memory region. Responsive to determining the memory region corresponds to an entry in the private region table, the mechanism performs a remote memory controller snoop of a remote memory controller without snooping the multiple processor system.

公开(公告)号：US09720831B2

公开(公告)日：2017-08-01

申请号：US14922042

申请日：2015-10-23

Applicant: Intel Corporation

Inventor： Karthikeyan Avudaiyappan ,  Mohammad Abdallah

IPC: G06F12/08 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0804 ,  G06F12/0897 ,  G06F12/12

CPC classification number: G06F12/0811 ,  G06F12/0804 ,  G06F12/0815 ,  G06F12/0897 ,  G06F12/12 ,  G06F2212/1016 ,  G06F2212/1032 ,  G06F2212/1048 ,  G06F2212/283 ,  G06F2212/608

Abstract: A method for maintaining the coherency of a store coalescing cache and a load cache is disclosed. As a part of the method, responsive to a write-back of an entry from a level one store coalescing cache to a level two cache, the entry is written into the level two cache and into the level one load cache. The writing of the entry into the level two cache and into the level one load cache is executed at the speed of access of the level two cache.

公开(公告)号：US20170185516A1

公开(公告)日：2017-06-29

申请号：US14980144

申请日：2015-12-28

Applicant: ARM Limited

Inventor： Ashley Miles STEVENS ,  Andrew David TUNE ,  Daniel Adam SARA

IPC: G06F12/08 ,  G06F9/30 ,  G06F15/80 ,  G06F15/78

CPC classification number: G06F12/0831 ,  G06F2212/1048

Abstract: A data processing apparatus having an interconnect circuit operable to transfer snoop messages between a plurality of connected devices, at least one of which has multiple ports each coupled to a local cache. The interconnect circuit has decode logic that identifies, from an address in a snoop message, which port is coupled to the local cache associated with the address, and the interconnect circuit transmits the snoop message to that port. The interconnect circuit may also have a snoop filter that stores a snoop vector for each block of data in the local caches. Each snoop vector has an address tag that identifies the block of data and a presence vector indicative of which devices of the connected devices have a copy of the block of data. The presence vector does not identify which port of a device has access to the copy.

公开(公告)号：US20170153987A1

公开(公告)日：2017-06-01

申请号：US14955150

申请日：2015-12-01

Applicant: International Business Machines Corporation

Inventor： Chetan L. Gaonkar ,  Keerthi B. Kumar

IPC: G06F12/14 ,  G06F9/455 ,  G06F12/10

CPC classification number: G06F12/145 ,  G06F3/0608 ,  G06F9/45558 ,  G06F12/0284 ,  G06F12/1009 ,  G06F2009/45583 ,  G06F2212/1048 ,  G06F2212/1056 ,  G06F2212/152 ,  G06F2212/656

Abstract: A physical address of a page may be identified. A first process that implements copy-on-read techniques for the page may be detected. A determination may be made that the first process is not expected to write to the page. In response to that determination, a different logical address may be established for the first process for the page from the logical address of a second process for the page, but the two logical addresses may be mapped to the same physical page.

公开(公告)号：US20170116118A1

公开(公告)日：2017-04-27

申请号：US14921468

申请日：2015-10-23

Applicant: QUALCOMM INCORPORATED

Inventor： ALAIN ARTIERI ,  SUBBARAO PALACHARLA ,  LAURENT MOLL ,  RAGHU SANKURATRI ,  Kedar Bhloe ,  Vinod Chamarty

IPC: G06F12/08

CPC classification number: G06F12/084 ,  G06F12/0842 ,  G06F12/0846 ,  G06F12/0864 ,  G06F12/0895 ,  G06F12/123 ,  G06F12/127 ,  G06F2212/1044 ,  G06F2212/1048 ,  G06F2212/601 ,  G06F2212/62

Abstract: A cache controller adaptively partitions a shared cache. The adaptive partitioning cache controller includes tag comparison and staling logic and selection logic that are responsive to client access requests and various parameters. A component cache is assigned a target occupancy which is compared to a current occupancy. A conditional identification of stale cache lines is used to manage data stored in the shared cache. When a conflict or cache miss is identified, selection logic identifies candidates for replacement preferably among cache lines identified as stale. Each cache line is assigned to a bucket with a fixed number of buckets per component cache. Allocated cache lines are assigned to a bucket as a function of the target occupancy. After a select number of buckets are filled, subsequent allocations result in the oldest cache lines being marked stale. Cache lines are deemed stale when their respective component cache active indicator is de-asserted.

公开(公告)号：US20170109080A1

公开(公告)日：2017-04-20

申请号：US15062855

申请日：2016-03-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Fei Liu ,  Yang Seok Ki ,  Xiling Sun

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F12/0842 ,  G06F12/109 ,  G06F2212/1048

Abstract: A computing system includes a memory module, including a memory bank and a memory rank; and a control unit, coupled to the memory module, configured to: determine a core memory affinity between an aggregated memory and a CPU core; designate the memory bank and the memory rank, from the aggregated memory, as a core affiliated memory for the CPU core based on the core memory affinity; and allocate a slab class from the core affiliated memory to an application program based on a core application affinity with the CPU core.

公开(公告)号：US20170075620A1

公开(公告)日：2017-03-16

申请号：US15122533

申请日：2014-04-24

Applicant: HITACHI, LTD.

Inventor： Akira YAMAMOTO ,  Junji OGAWA ,  Norio SHIMOZONO ,  Yoshihiro YOSHII ,  Kazuei HIRONAKA ,  Atsushi KAWAMURA

IPC: G06F3/06

CPC classification number: G06F3/0641 ,  G06F3/0608 ,  G06F3/0659 ,  G06F3/0688 ,  G06F11/1004 ,  G06F12/0246 ,  G06F12/084 ,  G06F12/0866 ,  G06F12/0871 ,  G06F12/0873 ,  G06F12/1009 ,  G06F12/109 ,  G06F17/30097 ,  G06F17/3015 ,  G06F2212/1044 ,  G06F2212/1048 ,  G06F2212/2022 ,  G06F2212/263 ,  G06F2212/466 ,  G06F2212/657

Abstract: A storage system according to the present invention has a plurality of flash packages equipped with a deduplication function. When a storage controller transmits a write data and a feature value of write data to a flash package, the flash package compares contents of the write data with data having a same feature value as the feature value of the write data. As a result of the comparison, if there is no corresponding data, the write data is stored in the flash memory, but if there is a corresponding data, the new data will not be stored. Thus, a greater number of data can be stored in the flash memory while preventing deterioration of performance.

Abstract translation: 根据本发明的存储系统具有配备有重复数据删除功能的多个闪存包。 当存储控制器将写入数据和写入数据的特征值发送到闪存包时，闪存包将写入数据的内容与具有与写入数据的特征值相同的特征值的数据进行比较。 作为比较的结果，如果没有对应的数据，写入数据被存储在闪存中，但是如果存在相应的数据，则不会存储新的数据。 因此，可以在闪速存储器中存储更多数量的数据，同时防止性能的恶化。

公开(公告)号：US20170068642A1

公开(公告)日：2017-03-09

申请号：US15356456

申请日：2016-11-18

Applicant: Softview L.L.C.

Inventor： Gary B. Rohrabaugh ,  Scott A. Sherman

IPC: G06F17/21 ,  G06F17/22 ,  G06F3/0488 ,  G06F17/30

CPC classification number: G06F17/211 ,  G06F3/0481 ,  G06F3/0488 ,  G06F9/451 ,  G06F17/2235 ,  G06F17/2247 ,  G06F17/30861 ,  G06F17/3087 ,  G06F17/3089 ,  G06F17/30896 ,  G06F17/30899 ,  G06F17/30902 ,  G06F17/30905 ,  G06F2203/04806 ,  G06F2212/1048 ,  G06Q30/02 ,  G09G5/24 ,  G09G2340/0407 ,  G09G2340/0492 ,  H04L67/02 ,  H04L67/04 ,  H04L67/2823

Abstract: Mobile devices enabled to support resolution-independent scalable display of Internet (Web) content to allow Web pages to be scaled (zoomed) and panned for better viewing on smaller screen sizes. The mobile devices employ software-based processing of original Web content, including HTML-based content, XML, cascade style sheets, etc. to generate scalable content. The scalable content and/or data derived therefrom are then employed to enable the Web content to be rapidly rendered, zoomed, and panned. Display lists may also be employed to provide further enhancements in rendering speed. Context zooms, including tap-based zooms on columns, images, and paragraphs are also enabled.

Abstract translation: 支持移动设备支持独立于分辨率的互联网（Web）内容的可扩展显示，以允许缩放（缩放）网页，并在较小的屏幕尺寸上进行更好的查看。 移动设备采用基于原始Web内容的软件处理，包括基于HTML的内容，XML，级联样式表等来生成可扩展内容。 然后使用可伸缩的内容和/或从其导出的数据来使Web内容能够快速呈现，缩放和平移。 还可以使用显示列表来进一步提高渲染速度。 上下文缩放，包括列，图像和段落上的基于点击的缩放也被启用。

公开(公告)号：US20170031815A1

公开(公告)日：2017-02-02

申请号：US14928790

申请日：2015-10-30

Applicant: Pradeep Varma

Inventor： Pradeep Varma

IPC: G06F12/02 ,  G06F12/12 ,  G06F12/08

CPC classification number: G06F12/0253 ,  G06F12/023 ,  G06F12/0261 ,  G06F12/0269 ,  G06F12/0891 ,  G06F12/12 ,  G06F2212/1024 ,  G06F2212/1044 ,  G06F2212/1048 ,  G06F2212/60

Abstract: Boxed pointers are disclosed, for all pointers, for safe and sequential or parallel use. Since a pointer box can be arbitrarily large, it supports any fat pointer encoding possible. The boxed pointers are managed out of the same heap or stack space as ordinary objects, providing scalability by a shared use of the entire program memory. The boxed pointers and objects are managed together by the same parallel, safe, memory management system including an optional precise, parallel garbage collector. To manage boxes independently of the garbage collector, explicit allocation and de-allocation means are provided including explicit killing of boxes using immediate or deferred frees. The entire system is constructed out of atomic registers as the sole shared memory primitive, avoiding all synchronization primitives and related expenses. Atomic pointer operations including pointer creation or deletion (malloc or free) are provided.

Abstract translation: 对于所有指针，公开了用于安全和顺序或并行使用的盒装指针。 由于指针盒可以任意大，它可以支持任何胖指针编码。 盒装指针由与普通对象相同的堆或堆栈空间进行管理，通过共享使用整个程序存储器提供可扩展性。 盒装指针和对象由同一个并行，安全的内存管理系统一起管理，包括可选的精确并行垃圾收集器。 为了独立于垃圾收集器管理盒子，提供明确的分配和解除分配手段，包括使用立即或延迟释放来显式杀死盒子。 整个系统由原子寄存器构建为唯一的共享存储器原语，避免所有同步原语和相关费用。 提供包括指针创建或删除（malloc或free）的原子指针操作。