利索-全球专利检索

  1. Login
  2. Sign Up

Search Results

338 records (took 0.026 seconds)

    System and method for reading and writing data with a shared memory hash table
    74.
    发明授权
    System and method for reading and writing data with a shared memory hash table 有权
    用共享内存哈希表读写数据的系统和方法

    公开(公告)号：US09495114B2

    公开(公告)日：2016-11-15

    申请号：US14270122

    申请日：2014-05-05

    Applicant: Hugh W. Holbrook ,  Duncan Stuart Ritchie ,  Sebastian Sapa

    Inventor： Hugh W. Holbrook ,  Duncan Stuart Ritchie ,  Sebastian Sapa

    IPC: G06F17/30 ,  G06F12/10 ,  G06F3/06 ,  H04L12/743

    CPC classification number: G06F3/065 ,  G06F3/0614 ,  G06F3/0638 ,  G06F3/0673 ,  G06F12/1027 ,  G06F17/30097 ,  G06F2003/0691 ,  G06F2212/507 ,  H04L45/7453

    Abstract: A method and apparatus of a device that reads and writes data using a shared memory hash table and a lookaside buffer is described. In an exemplary embodiment, a device locates a bucket for the data in a shared memory hash table, where a writer updates the shared memory hash table and a reader that is one of a plurality of readers reads from the shared memory hash table. The device further retrieves an initial value of a version of the bucket. If the initial value of the version is odd, the device copies the data from a lookaside buffer of the writer to a local buffer for the reader, wherein the lookaside buffer stores a copy of the data while the bucket is being modified.

    Abstract translation: 描述了使用共享存储器散列表和后备缓冲器来读取和写入数据的设备的方法和装置。 在示例性实施例中，设备将数据的桶定位在共享存储器散列表中，其中写入器更新共享存储器散列表，并且读取器是从多个读取器中的一个读取器从共享存储器散列表读取的。 设备进一步检索桶的版本的初始值。 如果版本的初始值是奇数，则设备将数据从写入器的后备缓冲器复制到读取器的本地缓冲器，其中后备缓冲器存储在修改存储桶时数据的副本。

    System and method for validation of cache memory locking
    76.
    发明授权
    System and method for validation of cache memory locking 有权
    用于高速缓存内存锁定验证的系统和方法

    公开(公告)号：US09268715B2

    公开(公告)日：2016-02-23

    申请号：US14188650

    申请日：2014-02-24

    Applicant: Puneet Aggarwal ,  Eswaran Subramaniam

    Inventor： Puneet Aggarwal ,  Eswaran Subramaniam

    IPC: G06F12/14

    CPC classification number: G06F12/1483 ,  G06F12/0864 ,  G06F12/126 ,  G06F2212/507

    Abstract: A cache lock validation apparatus for a cache having sets of cache lines and coupled to a cache controller. The apparatus includes a memory coupled to a processor. The memory includes test case data related to an architecture of the cache. The processor selects a first set of the sets of cache lines and generates a corresponding first group of addresses and an overflow status address. The processor instructs the cache controller to sequentially lock the first group of addresses and the overflow status address. The processor checks a status of an overflow bit in a status register of the cache controller upon locking the overflow status address, and generates a FAIL status signal when the overflow bit is reset.

    Abstract translation: 一种用于具有高速缓存线组并且耦合到高速缓存控制器的高速缓存的高速缓存锁确认装置。 该装置包括耦合到处理器的存储器。 存储器包括与缓存的体系结构有关的测试用例数据。 处理器选择第一组高速缓存行集合并且生成对应的第一组地址和溢出状态地址。 处理器指示高速缓存控制器顺序地锁定第一组地址和溢出状态地址。 在锁定溢出状态地址时，处理器检查高速缓存控制器的状态寄存器中的溢出位的状态，并在溢出位复位时产生FAIL状态信号。

    Speculative cache modification
    77.
    发明授权
    Speculative cache modification 有权
    推测缓存修改

    公开(公告)号：US09092346B2

    公开(公告)日：2015-07-28

    申请号：US13992354

    申请日：2011-12-22

    Applicant: James E. McCormick, Jr.

    Inventor： James E. McCormick, Jr.

    IPC: G06F9/38 ,  G06F12/08 ,  G06F9/30

    CPC classification number: G06F12/0875 ,  G06F9/30043 ,  G06F9/3842 ,  G06F12/0802 ,  G06F12/0855 ,  G06F2212/507 ,  Y02D10/13

    Abstract: In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for implementing a speculative cache modification design. For example, in one embodiment, such means may include an integrated circuit having a data bus; a cache communicably interfaced with the data bus; a pipeline communicably interfaced with the data bus, in which the pipeline is to receive a store instruction corresponding to a cache line to be written to cache; caching logic to perform a speculative cache write of the cache line into the cache before the store instruction retires from the pipeline; and cache line validation logic to determine if the cache line written into the cache is valid or invalid, in which the cache line validation logic is to invalidate the cache line speculatively written into the cache when determined invalid and further in which the store instruction is allowed to retire from the pipeline when the cache line is determined to be valid.

    Abstract translation: 根据本文公开的实施例，提供了用于实现推测性缓存修改设计的方法，系统，机制，技术和装置。 例如，在一个实施例中，这种装置可以包括具有数据总线的集成电路; 与数据总线可通信地连接的缓存; 与数据总线可通信地连接的流水线，其中流水线将接收与要写入高速缓存的高速缓存行相对应的存储指令; 高速缓存逻辑，以便在存储指令从流水线退出之前执行高速缓存行的推测高速缓存写入高速缓存; 和高速缓存行验证逻辑，以确定写入高速缓存的高速缓存行是否有效或无效，其中高速缓存行验证逻辑将在确定为无效时将推测性写入高速缓存的高速缓存行无效，并且进一步允许存储指令 当缓存行被确定为有效时从管道中退出。

    EFFICIENT FILL-BUFFER DATA FORWARDING SUPPORTING HIGH FREQUENCIES
    78.
    发明申请
    EFFICIENT FILL-BUFFER DATA FORWARDING SUPPORTING HIGH FREQUENCIES 有权
    高效的缓冲数据，支持高频率

    公开(公告)号：US20150186292A1

    公开(公告)日：2015-07-02

    申请号：US14337211

    申请日：2014-07-21

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Karthik SUNDARAM ,  Rama GOPAL ,  Murali CHINNAKONDA

    IPC: G06F12/10 ,  G06F12/08

    CPC classification number: G06F12/1045 ,  G06F9/3861 ,  G06F12/0811 ,  G06F12/0859 ,  G06F12/1009 ,  G06F2212/1024 ,  G06F2212/507

    Abstract: A Fill Buffer (FB) based data forwarding scheme that stores a combination of Virtual Address (VA), TLB (Translation Look-aside Buffer) entry# or an indication of a location of a Page Table Entry (PTE) in the TLB, and a TLB page size information in the FB and uses these values to expedite FB forwarding. Load (Ld) operations send their non-translated VA for an early comparison against the VA entries in the FB, and are then further qualified with the TLB entry# to determine a “hit.” This hit determination is fast and enables FB forwarding at higher frequencies without waiting for a comparison of Physical Addresses (PA) to conclude in the FB. A safety mechanism may detect a false hit in the FB and generate a late load cancel indication to cancel the earlier-started FB forwarding by ignoring the data obtained as a result of the Ld execution. The Ld is then re-executed later and tries to complete successfully with the correct data.

    Abstract translation: 一种基于填充缓冲器（FB）的数据转发方案，其存储虚拟地址（VA），TLB（翻译后备缓冲区）条目＃或页面表项（PTE）在TLB中的位置的指示的组合，以及 FB中的TLB页面大小信息，并使用这些值来加速FB转发。 加载（Ld）操作发送他们的非翻译的VA，以便与FB中的VA条目进行早期比较，然后进一步通过TLB条目＃进行限定，以确定“命中”。该命中确定速度很快，可以使FB转发 更高的频率，而不等待物理地址（PA）的比较结束于FB。 安全机制可以检测到FB中的错误命中，并产生一个晚期负载取消指示，以通过忽略由于执行Ld而获得的数据来取消较早启动的FB转发。 然后，Ld稍后重新执行，并尝试使用正确的数据成功完成。

    System and Method for Predicting False Sharing
    80.
    发明申请
    System and Method for Predicting False Sharing 有权
    用于预测虚假共享的系统和方法

    公开(公告)号：US20150032971A1

    公开(公告)日：2015-01-29

    申请号：US14341438

    申请日：2014-07-25

    Applicant: Futurewei Technologies, Inc.

    Inventor： Chen Tian ,  Tongping Liu ,  Ziang Hu

    IPC: G06F12/08

    CPC classification number: G06F12/0842 ,  G06F8/443 ,  G06F11/3003 ,  G06F11/3037 ,  G06F11/3065 ,  G06F11/3089 ,  G06F11/3093 ,  G06F11/3428 ,  G06F11/3466 ,  G06F11/3471 ,  G06F12/0844 ,  G06F2201/865 ,  G06F2201/885 ,  G06F2212/1016 ,  G06F2212/507

    Abstract: In one embodiment, a method for predicting false sharing includes running code on a plurality of cores and tracking potential false sharing in the code while running the code to produce tracked potential false sharing, where tracking the potential false sharing includes determining whether there is potential false sharing between a first cache line and a second cache line, and where the first cache line is adjacent to the second cache line. The method also includes reporting potential false sharing in accordance with the tracked potential false sharing to produce a false sharing report.

    Abstract translation: 在一个实施例中，一种用于预测虚假共享的方法包括：在多个核心上运行代码并在运行代码时跟踪代码中的潜在错误共享以产生跟踪的潜在虚假共享，其中跟踪潜在的虚假共享包括确定是否存在潜在的错误共享 在第一高速缓存行和第二高速缓存行之间共享，并且其中第一高速缓存行与第二高速缓存行相邻。 该方法还包括根据跟踪的潜在虚假共享报告潜在的虚假共享，以产生虚假共享报告。

Patent Agency Ranking