公开(公告)号：US11901438B2

公开(公告)日：2024-02-13

申请号：US17328674

申请日：2021-05-24

申请人： Adeia Semiconductor Solutions LLC

发明人： Kangguo Cheng ,  Juntao Li ,  Heng Wu ,  Peng Xu

IPC分类号： H01L29/00 ,  H01L29/66 ,  H01L29/06 ,  H01L29/40 ,  H01L29/78 ,  H01L21/311 ,  H01L29/423 ,  H01L23/31 ,  H01L23/29 ,  H01L21/02 ,  H01L29/786 ,  H01L29/775 ,  B82Y10/00

CPC分类号： H01L29/6656 ,  B82Y10/00 ,  H01L21/02164 ,  H01L21/02236 ,  H01L21/31116 ,  H01L23/291 ,  H01L23/3171 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/6681 ,  H01L29/66553 ,  H01L29/775 ,  H01L29/7853 ,  H01L29/78696

摘要： Inner and outer spacers for nanosheet transistors are formed using techniques that improve junction uniformity. One nanosheet transistor device includes outer spacers and an interlevel dielectric layer liner made from the same material. A second nanosheet transistor device includes outer spacers, inner spacers and an interlevel dielectric layer liner that are all made from the same material.

公开(公告)号：US11894425B2

公开(公告)日：2024-02-06

申请号：US18106001

申请日：2023-02-06

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Yun-Chi Wu ,  Tsung-Yu Yang ,  Cheng-Bo Shu ,  Chien Hung Liu

IPC分类号： H01L29/08 ,  H01L29/40 ,  H01L21/3213 ,  H01L21/265 ,  H01L21/266 ,  H01L21/311 ,  H01L29/66 ,  H01L21/027 ,  H01L21/8238 ,  H01L29/78 ,  H01L27/092 ,  H01L21/02 ,  H10B10/00

CPC分类号： H01L29/0847 ,  H01L21/0276 ,  H01L21/02164 ,  H01L21/266 ,  H01L21/2652 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32136 ,  H01L21/32139 ,  H01L21/823814 ,  H01L21/823828 ,  H01L27/092 ,  H01L29/401 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66545 ,  H01L29/7833 ,  H10B10/12

摘要： A method of forming a semiconductor arrangement includes forming a gate dielectric layer over a semiconductor layer. A gate electrode layer is formed over the gate dielectric layer. A first gate mask is formed over the gate electrode layer. The gate electrode layer is etched using the first gate mask as an etch template to form a first gate electrode. A first dopant is implanted into the semiconductor layer using the first gate mask and the first gate electrode as an implantation template to form a first doped region in the semiconductor layer.

公开(公告)号：US20240021501A1

公开(公告)日：2024-01-18

申请号：US18356031

申请日：2023-07-20

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Mrunal A. Khaderbad ,  Yasutoshi Okuno ,  Sung-Li Wang ,  Pang-Yen Tsai ,  Shen-Nan Lee ,  Teng-Chun Tsai

IPC分类号： H01L23/485 ,  H01L21/768 ,  H01L29/66 ,  H01L21/311 ,  H01L21/02 ,  H01L21/285 ,  H01L29/417 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/45 ,  H01L21/8238 ,  H01L23/532 ,  H01L23/528 ,  H01L29/08 ,  H01L29/41

CPC分类号： H01L23/485 ,  H01L21/76822 ,  H01L29/66795 ,  H01L21/76814 ,  H01L21/31116 ,  H01L21/02634 ,  H01L21/76847 ,  H01L21/76846 ,  H01L21/28562 ,  H01L29/41791 ,  H01L29/785 ,  H01L21/823431 ,  H01L29/66545 ,  H01L29/456 ,  H01L21/823821 ,  H01L21/76831 ,  H01L21/76826 ,  H01L23/532 ,  H01L23/528 ,  H01L29/0847 ,  H01L29/41 ,  H01L29/417 ,  H01L29/7848

摘要： A semiconductor device and a method of forming the same are provided. A method includes forming a gate over a semiconductor structure. An epitaxial source/drain region is formed adjacent the gate. A dielectric layer is formed over the epitaxial source/drain region. An opening extending through the dielectric layer and exposing the epitaxial source/drain region is formed. A conductive material is non-conformally deposited in the opening. The conductive material fills the opening in a bottom-up manner.

公开(公告)号：US20240021430A1

公开(公告)日：2024-01-18

申请号：US18366074

申请日：2023-08-07

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ming Chyi Liu ,  Hung-Wen Hsu ,  Min-Yung Ko

IPC分类号： H01L21/3065 ,  H01L23/522 ,  H01L21/66 ,  H01L21/67 ,  H01J37/32 ,  H01L21/306 ,  H01L21/3213 ,  H01L21/311

CPC分类号： H01L21/3065 ,  H01L23/5226 ,  H01L22/12 ,  H01L21/67253 ,  H01J37/32724 ,  H01L21/67069 ,  H01L21/30604 ,  H01L21/32136 ,  H01L21/32134 ,  H01L21/31116 ,  H01L21/31138 ,  H01J2237/334

摘要： A work piece is positioned on a work piece support, which includes a plurality of temperature control zones. A pre-etch surface topography is determined by measuring a plurality of pre-etch surface heights or thicknesses at a plurality of sites on the work piece. The plurality of sites correspond to the plurality of temperature control zones on the work piece support. At least a first zone of the temperature control zones is heated or cooled based on the measured plurality of pre-etch surface heights or thicknesses, so that the first zone has a first temperature different from a second temperature of a second zone of the temperature control zones. A dry etch is carried out while the first zone has the first temperature different from the second temperature of the second zone of the temperature control zones.

公开(公告)号：US11876046B2

公开(公告)日：2024-01-16

申请号：US16869096

申请日：2020-05-07

申请人： SK hynix Inc.

发明人： Ki Hong Lee

IPC分类号： H01L23/528 ,  H01L23/532 ,  H01L23/535 ,  H01L29/06 ,  H01L21/768 ,  H01L21/762 ,  H01L21/311 ,  H10B41/10 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H10B63/00 ,  H10N70/20 ,  H10N70/00 ,  H10B41/27 ,  H10B43/27

CPC分类号： H01L23/528 ,  H01L21/31116 ,  H01L21/762 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/535 ,  H01L23/53295 ,  H01L29/0649 ,  H10B41/10 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H10B63/30 ,  H10B63/845 ,  H10N70/231 ,  H10N70/25 ,  H10N70/823 ,  H10B41/27 ,  H10B43/27 ,  H10B63/34

摘要： A semiconductor device includes a wiring structure, a stacked structure located over the wiring structure, channel structures passing through the stacked structure, contact plugs passing through the stacked structure and electrically connected to the wiring structure, and insulating spacers each including loop patterns surrounding a sidewall of each of the contact plugs and stacked along the sidewall of each of the contact plugs.

公开(公告)号：US20240014040A1

公开(公告)日：2024-01-11

申请号：US18195498

申请日：2023-05-10

申请人： NANYA TECHNOLOGY CORPORATION

发明人： YING-CHENG CHUANG ,  YU-TING LIN

IPC分类号： H01L21/033 ,  H01L21/311 ,  H01L21/3065 ,  H01L21/027 ,  H01L21/3213 ,  H01L21/3205

CPC分类号： H01L21/0332 ,  H01L21/31138 ,  H01L21/3065 ,  H01L21/0337 ,  H01L21/0276 ,  H01L21/32135 ,  H01L21/31144 ,  H01L21/31116 ,  H01L21/32139 ,  H01L21/32055 ,  H01L21/76816

摘要： The present disclosure provides a method of manufacturing a semiconductor structure. A substrate is provided. A multi-layer structure is formed over the substrate, wherein the multi-layer structure includes a semiconductive material layer and an oxide layer over the semiconductive material layer. The oxide layer is patterned to form a first patterned layer. A second patterned layer is formed on the semiconductive material layer and alternately arranged with the first patterned layer. A first etching operation is performed on the substrate using a comprehensive pattern of the first patterned layer and the second patterned layer.

公开(公告)号：US20240014038A1

公开(公告)日：2024-01-11

申请号：US17859208

申请日：2022-07-07

申请人： NANYA TECHNOLOGY CORPORATION

发明人： YING-CHENG CHUANG ,  YU-TING LIN

IPC分类号： H01L21/033 ,  H01L21/027 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/3213

CPC分类号： H01L21/0332 ,  H01L21/0276 ,  H01L21/0337 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/32055 ,  H01L21/32139 ,  H01L21/32135 ,  H01L21/76816

摘要： The present disclosure provides a method of manufacturing a semiconductor structure. A substrate is provided. A multi-layer structure is formed over the substrate, wherein the multi-layer structure includes a semiconductive material layer and an oxide layer over the semiconductive material layer. The oxide layer is patterned to form a first patterned layer. A second patterned layer is formed on the semiconductive material layer and alternately arranged with the first patterned layer. A first etching operation is performed on the substrate using a comprehensive pattern of the first patterned layer and the second patterned layer.

公开(公告)号：US20240006253A1

公开(公告)日：2024-01-04

申请号：US17854561

申请日：2022-06-30

申请人： NANYA TECHNOLOGY CORPORATION

发明人： CHUN-SHUN HUANG

IPC分类号： H01L21/66 ,  H01L21/3213 ,  H01L21/311

CPC分类号： H01L22/32 ,  H01L22/20 ,  H01L21/32135 ,  H01L21/31116

摘要： A method of manufacturing semiconductor testing structure is provided. The method includes: providing a substrate; forming a first metal layer on the substrate, wherein the first metal layer comprises a plurality of fingers extending along a first direction; forming a dielectric structure on the first metal layer; and forming a plurality of second metal layers on the dielectric structure, wherein the first metal layer comprises a plurality of fingers extending along a first direction.

公开(公告)号：US20240006187A1

公开(公告)日：2024-01-04

申请号：US18247669

申请日：2021-10-28

申请人： Tokyo Electron Limited

发明人： Toshinori DEBARI ,  Reiko SASAHARA ,  Teppei OKUMURA ,  Woonghyun JEUNG ,  Kenshiro ASAHI ,  Hiroyuki ABE ,  Seungmin KIM

IPC分类号： H01L21/311 ,  H01L21/02 ,  H01L21/67

CPC分类号： H01L21/31116 ,  H01L21/0206 ,  H01L21/67069

摘要： An etching method includes: providing, to an interior of a chamber, a substrate having a three-layered film formed by stacking a first silicon oxide-based film, a silicon nitride-based film, and a second silicon oxide-based film; and collectively etching the three-layered film using a HF—NH3-based gas in the interior of the chamber while adjusting a gas ratio in each of the first silicon oxide-based film, the silicon nitride-based film, and the second silicon oxide-based film.

公开(公告)号：US20240006186A1

公开(公告)日：2024-01-04

申请号：US18036932

申请日：2021-07-28

申请人： Ajou University Industry-Academic Cooperation Foundation

发明人： Chang-Koo KIM ,  Jun-Hyun KIM ,  Sang-Hyun YOU

IPC分类号： H01L21/311 ,  H01J37/32

CPC分类号： H01L21/31116 ,  H01J37/32449 ,  H01J37/32522 ,  H01L21/31122 ,  H01J2237/334

摘要： Disclosed is a plasma etching method. The method includes a first step of vaporizing liquid heptafluoropropyl methyl ether (HFE-347mcc3) and liquid pentafluoropropanol (PFP); a second step of supplying a discharge gas containing the vaporized HFE-347mcc3, the vaporized PFP, and argon gas to a plasma chamber in which an etching target is disposed; and a third step of discharging the discharge gas to generate plasma and of plasma-etching the etching target using the generated plasma.