公开(公告)号：US09935646B2

公开(公告)日：2018-04-03

申请号：US14802787

申请日：2015-07-17

Applicant: Schweitzer Engineering Laboratories, Inc.

Inventor： Travis C. Mallett

IPC: H03M1/10 ,  H03M3/00 ,  G06F11/00

CPC classification number: H03M1/1076 ,  G06F11/00 ,  H03M1/1071 ,  H03M1/109 ,  H03M3/378 ,  H03M3/458

Abstract: The present disclosure provides systems and methods for identifying failures in an analog to digital (A/D) converter. An intelligent electronic device (IED) may monitor a digital output of one or more A/D converters. The IED may determine a slope value limit associated with the A/D converter. The IED may determine an output slope value of the digital output based on a difference of a converter output value measured at a first time and a converter output value measured at a later time. If the determined output slope value exceeds the slope value limit, the IED may identify a failure of the A/D converter. An IED may determine that concurrent failures in multiple, parallel A/D converters are indicative of a problem upstream from the A/D converters.

公开(公告)号：US20170134036A1

公开(公告)日：2017-05-11

申请号：US15332630

申请日：2016-10-24

Applicant: REALTEK SEMICONDUCTOR CORPORATION

Inventor： SHIH-HSIUNG HUANG

IPC: H03M1/10 ,  H03M1/46

CPC classification number: H03M1/109 ,  H03M1/466

Abstract: This invention discloses a method and a circuit for testing a successive approximation ADC. The test method includes the following steps: receiving a plurality of digital output codes of a SAR ADC; counting the number of odd numbers and the number of even numbers of the digital output codes; and determining whether an error occurs in the SAR ADC based on the number of odd numbers and the number of even numbers.

公开(公告)号：US20170099062A1

公开(公告)日：2017-04-06

申请号：US15282677

申请日：2016-09-30

Applicant: Infineon Technologies AG

Inventor： Dario Vagni ,  Peter Bogner ,  Jaafar Mejri

IPC: H03M1/10 ,  H03M1/12

CPC classification number: H03M1/1071 ,  H03M1/109 ,  H03M1/1245

Abstract: A method for use in testing an analog-to-digital converter. The method includes providing a set of bins, varying a voltage, taking samples of the voltage, providing a selection flag, associating each sample with one bin of the set of bins, and observing a number of samples associated with the bins. An apparatus includes an analog-to-digital converter configured to convert a voltage at an input node to a digital representation provided at an output node. The input node is configured to be coupled to a voltage generator. A sample select unit is configured to determine if a voltage at the input node at least equals a first threshold level and does not exceed a second threshold level. The apparatus is configured, based on the determining, to selectively associate the digital representation with a bin of a set of bins.

公开(公告)号：US09564914B1

公开(公告)日：2017-02-07

申请号：US15079521

申请日：2016-03-24

Applicant: Schweitzer Engineering Laboratories, Inc.

Inventor： Travis C. Mallett ,  Ben M. Armstrong

IPC: H03M1/10 ,  H03M1/34

CPC classification number: H03M1/1009 ,  H03M1/1038 ,  H03M1/109 ,  H03M1/12 ,  H03M1/34

Abstract: The present disclosure provides systems and methods for identifying changes in and failures of a reference voltage of an analog to digital (A/D) converter. A non-scalar function of the reference voltage of the A/D converter can be determined and output to the A/D converter. The A/D converter is configured to output a digital value to the A/D conversion system, wherein the digital value corresponds to the non-scalar function of the reference voltage. The A/D conversion system decodes the non-scalar function of the reference voltage with a corresponding inverse function, and may determine the drift factor associated with the reference voltage. The A/D conversion system can report a change in, or a failure of, the A/D converter or its reference voltage, and can operate or prevent operation of protection elements.

Abstract translation: 本公开提供用于识别模数（A / D）转换器的参考电压的变化和失败的系统和方法。 可以确定A / D转换器的参考电压的非标量函数并将其输出到A / D转换器。 A / D转换器被配置为向A / D转换系统输出数字值，其中数字值对应于参考电压的非标量函数。 A / D转换系统用对应的反函数对参考电压的非标量函数进行解码，并且可以确定与参考电压相关的漂移因子。 A / D转换系统可以报告A / D转换器或其参考电压的变化或故障，并可以操作或防止保护元件的工作。

公开(公告)号：US09325337B1

公开(公告)日：2016-04-26

申请号：US14593591

申请日：2015-01-09

Applicant: ANALOG DEVICES GLOBAL

Inventor： Dennis A. Dempsey

IPC: H03M1/10 ,  H03M1/66

CPC classification number: H03M1/109 ,  H03M1/1038 ,  H03M1/66

Abstract: In contrast to some existing techniques, a calibration technique compares multiple outputs which may be, for example, successive or different outputs from the digital-to-analog converter (DAC) in an analog environment and determines differences between at least two outputs in an analog environment. A feedback signal is provided in the digital environment to provide an internal or self-calibration regime. The digital feedback signal is provided to a digital signal processing (DSP) component of the calibration circuitry which uses the feedback signal to determine appropriate input codes to provide to the DAC. The same DAC can be used for both signal generation and feedback DAC purposes, and this provides a self-calibration of the DAC performance which is typically related to the integral non-linearity (INL) characteristics of the DAC transfer function.

Abstract translation: 与一些现有技术相比，校准技术比较多个输出，其可以是例如模拟环境中的数模转换器（DAC）的连续或不同的输出，并且确定模拟的至少两个输出之间的差异 环境。 在数字环境中提供反馈信号以提供内部或自校准方式。 将数字反馈信号提供给校准电路的数字信号处理（DSP）部件，其使用反馈信号来确定适当的输入代码以提供给DAC。 相同的DAC可用于信号发生和反馈DAC用途，并且这提供了DAC性能的自校准，其通常与DAC传递函数的积分非线性（INL）特性相关。

公开(公告)号：US09281831B2

公开(公告)日：2016-03-08

申请号：US14201624

申请日：2014-03-07

Applicant: Integrated Device Technology, Inc.

Inventor： Herve Marie ,  Arnaud Biallais

IPC: H03M1/06 ,  H03M1/00 ,  H03M1/18

CPC classification number: H03M1/002 ,  H03M1/1052 ,  H03M1/109 ,  H03M1/164 ,  H03M1/183

Abstract: Embodiments of a pipeline analog-to-digital converter is provided. In accordance with some embodiments, a pipeline analog-to-digital converter includes a stage, the stage including a residue amplifier that amplifies a residual voltage generated by the stage to obtain an amplified residual voltage; a backend digitizer that digitizes the amplified residual voltage to generate a digitized residual; and a digital correction circuit that corrects the digitized residual according to which zone the digitized residual is found.

Abstract translation: 提供了一种管线模数转换器的实施例。 根据一些实施例，管线模数转换器包括一个级，该级包括一个残余放大器，放大该级产生的残余电压以获得放大的残余电压; 后置数字转换器，其将放大的残余电压数字化以产生数字化残差; 以及数字校正电路，根据哪个区域找到数字化残差来校正数字化残差。

公开(公告)号：US09258006B2

公开(公告)日：2016-02-09

申请号：US14711733

申请日：2015-05-13

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takashi Oshima ,  Tatsuji Matsuura ,  Yuichi Okuda ,  Hideo Nakane ,  Takaya Yamamoto ,  Keisuke Kimura

IPC: H03M1/06 ,  H03M1/12 ,  H03M1/10 ,  H03M1/00 ,  H03M1/44 ,  H03M1/38 ,  H03M1/46

CPC classification number: H03M1/1245 ,  H03M1/002 ,  H03M1/0609 ,  H03M1/0639 ,  H03M1/1038 ,  H03M1/109 ,  H03M1/14 ,  H03M1/38 ,  H03M1/44 ,  H03M1/46 ,  H03M1/56

Abstract: A digital-correction-type A/D converter which is a charge sharing type and performing successive approximation is realized in a small area. The A/D converter is configured with an A/D conversion unit which is a charge sharing type and performing successive approximation, a digital correction unit which receives a digital output of the A/D conversion unit and performs digital correction to the digital output, and a holding unit which holds a test signal. A test signal of a common value from the holding unit is inputted into the A/D conversion unit in the first period and the second period. The A/D conversion correction coefficient for the digital correction unit is calculated on the basis of the digital correction result of the digital correction unit in the first period, and the digital correction result of the digital correction unit in the second period.

公开(公告)号：US20150256193A1

公开(公告)日：2015-09-10

申请号：US14711733

申请日：2015-05-13

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takashi OSHIMA ,  Tatsuji MATSUURA ,  Yuichi OKUDA ,  Hideo NAKANE ,  Takaya YAMAMOTO ,  Keisuke KIMURA

IPC: H03M1/12 ,  H03M1/44 ,  H03M1/06 ,  H03M1/00

CPC classification number: H03M1/1245 ,  H03M1/002 ,  H03M1/0609 ,  H03M1/0639 ,  H03M1/1038 ,  H03M1/109 ,  H03M1/14 ,  H03M1/38 ,  H03M1/44 ,  H03M1/46 ,  H03M1/56

Abstract: A digital-correction-type A/D converter which is a charge sharing type and performing successive approximation is realized in a small area. The A/D converter is configured with an A/D conversion unit which is a charge sharing type and performing successive approximation, a digital correction unit which receives a digital output of the A/D conversion unit and performs digital correction to the digital output, and a holding unit which holds a test signal. A test signal of a common value from the holding unit is inputted into the A/D conversion unit in the first period and the second period. The A/D conversion correction coefficient for the digital correction unit is calculated on the basis of the digital correction result of the digital correction unit in the first period, and the digital correction result of the digital correction unit in the second period.

Abstract translation: 在小区域中实现了作为电荷共享型并进行逐次逼近的数字校正型A / D转换器。 A / D转换器配置有作为电荷共享型的A / D转换单元并执行逐次逼近，数字校正单元接收A / D转换单元的数字输出并对数字输出执行数字校正， 以及保持测试信号的保持单元。 来自保持单元的公共值的测试信号在第一周期和第二周期中被输入到A / D转换单元。 基于第一周期中的数字校正单元的数字校正结果和第二周期中的数字校正单元的数字校正结果来计算数字校正单元的A / D转换校正系数。

公开(公告)号：US20150256190A1

公开(公告)日：2015-09-10

申请号：US14630422

申请日：2015-02-24

Applicant: FUJITSU SEMICONDUCTOR LIMITED

Inventor： Takeshi TAKAYAMA

IPC: H03M1/06 ,  H03M1/66 ,  H03M1/12

CPC classification number: H03M1/1033 ,  H03M1/109 ,  H03M1/468

Abstract: An analog-to-digital conversion circuit includes capacitors coupled to a common line. Each capacitor has a capacitance less than or equal to a capacitance sum of lower order capacitors. Switches selectively supply an analog input signal, a first reference voltage, or a second reference voltage to the capacitors in response to a control signal. A reset switch supplies the common line with a first voltage between the first and second reference voltages. A comparator compares the first voltage with a second voltage at the common line to generate a determination signal. A conversion control circuit generates the control signal and a multiple-bit digital signal based on the determination signal. A measurement control circuit measures the capacitance of the capacitor corresponding to an upper order bit of the digital signal using lower order capacitors. A correction circuit corrects the digital signal based on the measured capacitance to generate a digital output signal.

Abstract translation: 模拟 - 数字转换电路包括耦合到公共线路的电容器。 每个电容器的电容小于或等于低阶电容器的电容和。 响应于控制信号，开关选择性地向电容器提供模拟输入信号，第一参考电压或第二参考电压。 复位开关为第一和第二参考电压之间的第一电压提供公共线。 比较器将第一电压与公共线上的第二电压进行比较以产生确定信号。 转换控制电路基于确定信号产生控制信号和多位数字信号。 测量控制电路使用低阶电容器测量对应于数字信号的高位的电容器的电容。 校正电路根据所测量的电容校正数字信号以产生数字输出信号。

公开(公告)号：US20150256189A1

公开(公告)日：2015-09-10

申请号：US14201624

申请日：2014-03-07

Applicant: Integrated Device Technology, Inc.

Inventor： Herve Marie ,  Arnaud Biallais

IPC: H03M1/00 ,  H03M1/18

CPC classification number: H03M1/002 ,  H03M1/1052 ,  H03M1/109 ,  H03M1/164 ,  H03M1/183

Abstract: Embodiments of a pipeline analog-to-digital converter is provided. In accordance with some embodiments, a pipeline analog-to-digital converter includes a stage, the stage including a residue amplifier that amplifies a residual voltage generated by the stage to obtain an amplified residual voltage; a backend digitizer that digitizes the amplified residual voltage to generate a digitized residual; and a digital correction circuit that corrects the digitized residual according to which zone the digitized residual is found.

Abstract translation: 提供了一种管线模数转换器的实施例。 根据一些实施例，管线模数转换器包括一个级，该级包括一个残余放大器，放大该级产生的残余电压以获得放大的残余电压; 后置数字转换器，其将放大的残余电压数字化以产生数字化残差; 以及数字校正电路，根据哪个区域找到数字化残差来校正数字化残差。