公开(公告)号：US20180159066A1

公开(公告)日：2018-06-07

申请号：US15525500

申请日：2015-12-17

Applicant: BOE TECHNOLOGY GROUP CO., LTD. ,  HEFEI BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.

Inventor： Yi KONG ,  Junhao LIU ,  Hongwei XUE ,  Qingsong XU ,  Lu LIU

IPC: H01L51/52 ,  H01L21/70 ,  H01L21/475 ,  H01L27/12

Abstract: An array substrate, a display panel, a display device, a method for manufacturing the array substrate and a method for manufacturing the display panel are provided. The array substrate includes a base substrate, and an organic layer and a passivation layer arranged above the base substrate. The base substrate includes a display region and a non-display region surrounding the display region. Each of the organic layer and the passivation layer is arranged in both the display region and the non-display region. A groove is arranged in the organic layer and the passivation layer in the non-display region, the groove penetrates the organic layer and the passivation layer and is of a closed pattern surrounding the display region. The groove is to be filled with a sealing material.

公开(公告)号：US09978870B2

公开(公告)日：2018-05-22

申请号：US14949664

申请日：2015-11-23

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kuo-Cheng Ching ,  Chao-Hsiung Wang ,  Chi-Wen Liu ,  Guan-Lin Chen

IPC: H01L21/70 ,  H01L29/772 ,  H01L21/336 ,  H01L21/335 ,  H01L29/78 ,  H01L29/66 ,  H01L29/161 ,  H01L29/165 ,  H01L21/762 ,  H01L29/10 ,  H01L29/06 ,  H01L29/16

CPC classification number: H01L29/7849 ,  H01L21/76205 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/785

Abstract: A fin structure suitable for a FinFET and having a buried insulator layer is disclosed. In an exemplary embodiment, a semiconductor device comprises a substrate with a first semiconductor material and having a fin structure formed thereupon. The fin structure includes a lower region proximate to the substrate, a second semiconductor material disposed on the lower region, a third semiconductor material disposed on the second semiconductor material, and an insulating material selectively disposed on the second semiconductor material such that the insulating material electrically isolates a channel region of the fin structure and further such that the insulating material exerts a strain on the channel region. The semiconductor device further comprises an isolation feature disposed adjacent to the fin structure.

公开(公告)号：US09972616B2

公开(公告)日：2018-05-15

申请号：US14909980

申请日：2013-09-27

Applicant: INTEL CORPORATION

Inventor： Walid Hafez ,  Chen-Guan Lee ,  Chia-Hong Jan

IPC: H01L21/70 ,  H01L21/20 ,  H01L27/06 ,  H01L49/02 ,  H01L29/66 ,  H01L29/775 ,  H01C7/06 ,  H01C17/232

CPC classification number: H01L27/0629 ,  H01C7/06 ,  H01C17/232 ,  H01L28/20 ,  H01L28/24 ,  H01L29/66439 ,  H01L29/66469 ,  H01L29/775

Abstract: Methods of forming resistor structures with tunable temperature coefficient of resistance are described. Those methods and structures may include forming an opening in a resistor material adjacent source/drain openings on a device substrate, forming a dielectric material between the resistor material and the source/drain openings, and modifying the resistor material, wherein a temperature coefficient resistance (TCR) of the resistor material is tuned by the modification. The modifications include adjusting a length of the resistor, forming a compound resistor structure, and forming a replacement resistor.

公开(公告)号：US20180122932A1

公开(公告)日：2018-05-03

申请号：US15795941

申请日：2017-10-27

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Xiaming ZHU

IPC: H01L29/786 ,  H01L21/70

CPC classification number: H01L29/786 ,  H01L21/707 ,  H01L27/1225 ,  H01L27/127 ,  H01L2021/775

Abstract: The present disclosure provides a TFT, a manufacturing method thereof, an array substrate and a display device. The TFT includes an N-type metal oxide TFT and a P-type metal oxide TFT. The manufacturing method includes a step of forming an active layer of the N-type metal oxide TFT and an active layer of a P-type metal oxide TFT on a base substrate through a single patterning process.

公开(公告)号：US09953986B2

公开(公告)日：2018-04-24

申请号：US14137879

申请日：2013-12-20

Applicant: INTEL CORPORATION

Inventor： Yih Wang

IPC: H01L21/70 ,  H01L27/11 ,  G11C11/419

CPC classification number: H01L27/1104 ,  G11C11/419

Abstract: Described is a 6T SRAM cell which comprises: a first n-type transistor with a gate terminal coupled to word-line, source/drain terminal coupled to a first bit-line and drain/source terminal coupled to a first node; and a second n-type transistor with a source terminal coupled to a first supply node, a drain terminal coupled to the first node, and a gate terminal for coupling to multiple terminals, wherein the gate terminal includes a capacitor to increase coupling capacitance of the second n-type transistor. Described is a method which comprises: forming a metal gate in a first direction; forming a first spacer in the first direction on one side of the metal gate, the first spacer having a first dimension; and forming a second spacer in the first direction on another side of the metal gate, the second spacer having a second dimension which is substantially different from the first dimension.

公开(公告)号：US09935103B2

公开(公告)日：2018-04-03

申请号：US15392693

申请日：2016-12-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L21/70 ,  H01L27/088 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/3105 ,  H01L21/02 ,  H01L21/3213 ,  H01L29/06 ,  H01L29/49 ,  H01L29/51 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L27/0886 ,  H01L21/02164 ,  H01L21/31055 ,  H01L21/32137 ,  H01L21/32139 ,  H01L21/76229 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/823864 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/42376 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6681

Abstract: A semiconductor device includes first and second Fin FET and a separation plug made of an insulating material and disposed between the first and second Fin FETs. The first Fin FET includes a first fin structure extending in a first direction, a first gate dielectric formed over the first fin structure and a first gate electrode formed over the first gate dielectric and extending a second direction perpendicular to the first direction. The second Fin FET includes a second fin structure, a second gate dielectric formed over the second fin structure and a second gate electrode formed over the first gate dielectric and extending the second direction. In a cross section a maximum width of the separation plug is located at a height Hb, which is less than ¾ of a height Ha of the separation plug.

公开(公告)号：US09922866B2

公开(公告)日：2018-03-20

申请号：US14815314

申请日：2015-07-31

Applicant: International Business Machines Corporation

Inventor： Stephen W. Bedell ,  Stephan A. Cohen ,  Joel P. de Souza ,  Karen A. Nummy ,  Daniel J. Poindexter ,  Devendra K. Sadana

IPC: H01L21/70 ,  H01L29/66 ,  H01L21/762 ,  H01L21/324

CPC classification number: H01L21/76251 ,  H01L21/324

Abstract: A silicon buffer layer selected from undoped silicon, p-doped silicon or a multilayered stack of, in any order, undoped silicon and p-doped silicon is provided between an n+ silicon layer and an oxide layer of an SOI substrate. The presence of the silicon buffer layer reduces electron injection into the oxide layer during device processing which requires an electric field.

公开(公告)号：US20180068832A1

公开(公告)日：2018-03-08

申请号：US15558888

申请日：2015-03-27

Applicant: Sakai Display Products Corporation

Inventor： Atsushi SHOJI

IPC: H01J37/32 ,  C23C16/54 ,  H01L21/70 ,  H01L21/3065 ,  H01L21/31

CPC classification number: H01J37/32009 ,  C23C16/4405 ,  C23C16/54 ,  H01L21/02 ,  H01L21/205 ,  H01L21/3065 ,  H01L21/31 ,  H01L21/707

Abstract: An example film forming device is provided with: a chamber for forming a film on a substrate; a supply tube for supplying a cleaning gas to the chamber; and a plasma generating unit, which is provided to the supply tube, and which generates plasma from the cleaning gas. The film forming device is characterized by being provided with: a temperature control unit that controls the temperature of the supply tube to temperature equal to or higher than a predetermined temperature; and a supply unit which supplies, each time when a previously set time equal to or shorter than 36 hours elapses, the chamber with the plasma thus generated by the plasma generating unit.

公开(公告)号：US09905488B2

公开(公告)日：2018-02-27

申请号：US14908455

申请日：2015-09-11

Applicant: BOE TECHNOLOGY GROUP CO., LTD. ,  CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.

Inventor： Haoyuan Fan ,  Yanxia Xin ,  Yuqing Yang

IPC: H01L23/58 ,  H01L29/04 ,  H01L27/12 ,  H01L21/70 ,  H01L21/66

CPC classification number: H01L22/32 ,  H01L22/14 ,  H01L27/1244 ,  H01L27/1259

Abstract: The present disclosure provides an array substrate, its manufacturing method and a display device. The array substrate includes operating circuit interfaces, testing interfaces, and testing lines connecting the operating circuit interfaces and the testing interfaces. Each testing line includes at least one cut-off point, and conductive contacts extending to an upper surface of the array substrate are arranged at two sides of each cut-off point of the testing line. When testing an operating circuit, electrically connecting the conductive contacts at two sides of each cut-off point enables the testing line to be conductive.

公开(公告)号：US09899415B1

公开(公告)日：2018-02-20

申请号：US15239230

申请日：2016-08-17

Applicant: International Business Machines Corporation

Inventor： Jin Cai ,  Jean-Olivier Plouchart

IPC: H01L21/70 ,  H01L27/01 ,  H01L27/12 ,  H01L21/84 ,  H01L21/027 ,  H01L21/762 ,  H01L21/306 ,  H01L21/02

CPC classification number: H01L27/1203 ,  H01L21/02238 ,  H01L21/0273 ,  H01L21/30604 ,  H01L21/30625 ,  H01L21/76254 ,  H01L21/84 ,  H01L27/13

Abstract: A radio frequency fully depleted silicon on insulator (RF-FDSOI) device and method of fabrication are provided. A silicon wafer for digital circuits is constructed using fully depleted silicon on insulator technology having a thin buried oxide layer. Localized areas of the silicon wafer are constructed for radio frequency circuits and/or passive devices. The silicon wafer has a silicon substrate having a resistivity greater than 1 KΩ·cm. The localized areas of the silicon wafer may include a trap rich layer implanted underneath a thin buried oxide layer. The localized areas of the silicon wafer may include a buried oxide layer that is thicker than the thin buried oxide layer. The thicker oxide layer is between 20 and 2000 nm thick. The localized areas of the silicon wafer may include a trap rich layer implanted underneath the thicker buried oxide layer.