公开(公告)号：US20180183457A1

公开(公告)日：2018-06-28

申请号：US15849234

申请日：2017-12-20

Applicant: Avnera Corporation

Inventor： Wai Lee ,  Jianping Wen ,  Garry N. Link

IPC: H03M1/46 ,  H03M1/44 ,  H03M1/08

CPC classification number: H03M1/462 ,  H03M1/0678 ,  H03M1/08 ,  H03M1/0863 ,  H03M1/442 ,  H03M1/468

Abstract: The disclosure includes a mechanism for mitigating charge related disturbances in a Successive Approximation Register (SAR) Analog to Digital Converter (ADC) by providing a fine reference connection and a rough reference connection. A switch array is activated to couple a current bit capacitor of a capacitor array to the rough reference connection while a current bit corresponding to the current bit capacitor is determined by a comparator. The switch array is further activated to couple a previous bit capacitor of the capacitor array to the fine reference connection while the current bit capacitor is coupled to the rough reference connection. This separates charge flow on the rough reference connection from capacitors coupled to the fine reference connection.

公开(公告)号：US20180183454A1

公开(公告)日：2018-06-28

申请号：US15832503

申请日：2017-12-05

Applicant: Avnera Corporation

Inventor： Wai Lee ,  Garry N. Link

IPC: H03M1/46 ,  H03M1/06 ,  H03M1/14 ,  H03M1/80 ,  H03M1/16

CPC classification number: H03M1/462 ,  H03M1/0626 ,  H03M1/0695 ,  H03M1/124 ,  H03M1/145 ,  H03M1/164 ,  H03M1/181 ,  H03M1/468 ,  H03M1/806

Abstract: The disclosure includes a successive approximation register (SAR) analog to digital converter (ADC). The SAR ADC includes a sampling network to store a sample of an analog signal. The SAR ADC also includes a comparator to successively compare the sample to reference values to determine a digital value corresponding to the sample of the analog signal. The comparator employs a plurality of comparator preamplifiers. The comparator also includes a programmable trim filter. The programmable trim filter is selectively set to adjust a bandwidth of the comparator preamplifiers to a bandwidth value corresponding with a preamplifier settling time subceeding a preamplifier settling threshold.

公开(公告)号：US20180174583A1

公开(公告)日：2018-06-21

申请号：US15706178

申请日：2017-09-15

Applicant: Avnera Corporation

Inventor： Xudong Zhao ,  Alexander C. Stange ,  Shawn O'Connor ,  Ali Hadiashar

IPC: G10L15/22 ,  G10L25/78 ,  G10L25/84 ,  H03M3/00

CPC classification number: G10L15/22 ,  G10L25/78 ,  G10L25/84 ,  G10L2015/088 ,  G10L2025/783 ,  H03M3/458

Abstract: A system for detecting and capturing voice commands, the system comprising a voice-activity detector (VAD) configured to receive a VAD-received digital-audio signal; determine the amplitude of the VAD-received digital-audio signal; compare the amplitude of the VAD-received digital-audio signal to a first threshold and to a second threshold; withhold a VAD interrupt signal when the amplitude of the VAD-received digital-audio signal does not exceed the first threshold or the second threshold; generate the VAD interrupt signal when the amplitude of the VAD-received digital-audio signal exceeds the first threshold and the second threshold; and perform spectral analysis of the VAD-received digital-audio signal when the amplitude of the VAD-received digital-audio signal is between the first threshold and the second threshold.

公开(公告)号：US20180167728A1

公开(公告)日：2018-06-14

申请号：US15895591

申请日：2018-02-13

Applicant: Avnera Corporation

Inventor： Amit Kumar ,  Thomas Irrgang ,  Xudong Zhao

IPC: H04R3/00 ,  G10K11/178

CPC classification number: H04R3/005 ,  G10K11/178 ,  G10K2210/3028 ,  G10K2210/3051 ,  G10K2210/3056 ,  H04R1/1083 ,  H04R2410/05

Abstract: An audio system can include an analog portion having multiple input sensors and an output device, a first digital portion running at a first rate and having a first processor that is electrically coupled with the input sensors and the output device, and a second digital portion running at a second rate that is higher than the first rate and having a second processor that is electrically coupled with the first processor.

公开(公告)号：US09985640B1

公开(公告)日：2018-05-29

申请号：US15793839

申请日：2017-10-25

Applicant: Avnera Corporation

Inventor： Jianping Wen ,  Gordon Ueki

IPC: H03M1/38 ,  H03M1/10 ,  H03M1/46

CPC classification number: H03M1/1009 ,  H03M1/462 ,  H03M1/466

Abstract: The disclosure includes an analog to digital converter (ADC) comprising a successive approximation register (SAR) unit including a capacitive network to take a sample of an analog signal and a comparator to approximate a digital value based on the analog signal sample via successive comparison. The disclosure also includes a programmable sequencer. The sequencer includes a control memory containing control signal states indicating control signals to operate the SAR unit. The sequencer also includes a program memory including sequence instructions defining a duty cycle for the SAR unit by referencing the control signal states in the control memory. The sequencer also includes a processing circuit to apply control signals according to the control signal states in an order defined by the sequence instructions to manage a sequence of operations at the SAR unit according to the duty cycle to control the ADC.

公开(公告)号：US09967647B2

公开(公告)日：2018-05-08

申请号：US14850859

申请日：2015-09-10

Applicant: Avnera Corporation

Inventor： Amit Kumar ,  Eric Sorensen ,  Shankar Rathoud

IPC: H04R1/10 ,  G10K11/178 ,  H04R3/00 ,  H04R29/00

CPC classification number: H04R1/1041 ,  G10K11/178 ,  G10K11/17855 ,  G10K2210/1081 ,  G10K2210/3021 ,  H04R1/1083 ,  H04R3/00 ,  H04R29/00 ,  H04R2410/05 ,  H04R2460/03

Abstract: A headphone detector including a headphone and a processor. The headphone has a microphone and a speaker, and the microphone is configured to generate an audio signal based on an output of the speaker. The processor is configured to receive the audio signal, determine a characteristic of the audio signal, and assess whether the headphone is on ear or off ear based on a comparison of the characteristic to a threshold. In another aspect, an off-ear detection (OED) system includes a headphone and an OED processor. The headphone has a speaker, a feedforward microphone, and a feedback microphone. The OED processor is configured to determine whether the headphone is off ear or on ear, based at least in part on a headphone audio signal, a feedforward microphone signal, and a feedback microphone signal.

公开(公告)号：US20180124517A1

公开(公告)日：2018-05-03

申请号：US15795721

申请日：2017-10-27

Applicant: Avnera Corporation

Inventor： Manpreet S. Khaira ,  David McNeill ,  Eric Sorensen ,  Sydney Newton

IPC: H04R5/04 ,  H04R5/033 ,  B23P19/04

CPC classification number: H04R5/04 ,  B23P19/04 ,  H04R1/1025 ,  H04R5/033 ,  H04R2460/01 ,  H04R2460/15

Abstract: The disclosure includes a headset including one or more earphones and a connector configured to couple data and charge between the headset and a user equipment (UE). The headset also includes a charge node. The charge node includes a charge port for receiving UE charge from a charge source. The charge node also includes a downstream port for coupling audio data toward the earphones. The charge node further includes an upstream port for coupling the audio data toward the earphones via the downstream port and coupling UE charge from the charge port toward the UE via the connector.

公开(公告)号：US20180054297A1

公开(公告)日：2018-02-22

申请号：US15799473

申请日：2017-10-31

Applicant: AVNERA CORPORATION

Inventor： Samuel J. Peters, II ,  Eric P. Etheridge ,  Victor Lee Hansen ,  Alexander C. Stange

IPC: H04L7/033 ,  H04L7/00

CPC classification number: H04L7/033 ,  G06F13/4295 ,  H04L7/0029 ,  H04L7/02

Abstract: A system can include a digital oversampler configured to oversample an input data stream; a rate generator configured to select a frequency that is not less than an expected frequency of the input data stream; a rate generator clock of the rate generator configured to output a clock signal that has the selected frequency; a sample receiver configured to receive at least one sample of the input data stream from the digital oversampler; a sample counter configured to be incremented by each received sample responsive to a determination that the sample receiver has received at least one sample of the input data stream from the digital oversampler; a sample rate converter configured to accumulate samples from the sample receiver at the rate of a “toothless” clock signal, wherein the sample counter is configured to be decremented by the “toothless” clock signal at the selected frequency responsive to a determination that the sample receiver has not received at least one sample of the input data stream from the digital oversampler; and an AND gate configured to pass the “toothless” clock signal to the sample rate converter responsive to a determination that an output of the sample counter is greater than zero.

公开(公告)号：US20180041196A1

公开(公告)日：2018-02-08

申请号：US15786500

申请日：2017-10-17

Applicant: Avnera Corporation

Inventor： Xudong Zhao

IPC: H03H17/06 ,  H03M13/27 ,  H03M13/00 ,  H03M7/00 ,  H03H17/02 ,  G10L21/0316 ,  G10L21/0356 ,  H03M13/33 ,  H03M5/00 ,  G10L19/00 ,  G10L19/24

CPC classification number: H03H17/0628 ,  G10L19/00 ,  G10L19/24 ,  G10L21/0316 ,  G10L21/0356 ,  G10L2019/001 ,  H03H17/028 ,  H03M5/00 ,  H03M7/00 ,  H03M13/00 ,  H03M13/27 ,  H03M13/33

Abstract: Embodiments of the invention may be used to implement a rate converter that includes: 6 channels in forward (audio) path, each channel having a 24-bit signal path per channel, an End-to-end SNR of 110 dB, all within the 20 Hz to 20 KHz bandwidth. Embodiment may also be used to implement a rate converter having: 2 channels in a reverse path, such as for voice signals, 16-bit signal path per channel, an End-to-end SNR of 93 dB, all within 20 Hz to 20 KHz bandwidth. The rate converter may include sample rates such as 8, 11.025, 12, 16, 22.05, 24, 32 44.1, 48, and 96 KHz. Further, rate converters according to embodiments may include a gated clock in low-power mode to conserve power.

公开(公告)号：US20180020281A1

公开(公告)日：2018-01-18

申请号：US15442619

申请日：2017-02-24

Applicant: Avnera Corporation

Inventor： Michael Jon Wurtz ,  Eric Sorensen

IPC: H04R1/10 ,  A61F11/08 ,  H04R23/00 ,  G10K11/178

CPC classification number: H04R1/1083 ,  A61F11/08 ,  G10K11/178 ,  G10K11/17857 ,  G10K11/17881 ,  G10K2210/1081 ,  G10K2210/3026 ,  G10K2210/3027 ,  G10K2210/3028 ,  G10K2210/3219 ,  G10K2210/3226 ,  H04R1/1016 ,  H04R23/006 ,  H04R2201/003 ,  H04R2410/05 ,  H04R2460/01

Abstract: Automatic noise-reduction (ANR) headsets include circuitry that cancels or suppress undesired noises. Recent years have seen the emergence of in-the-ear (ITE) earphones that incorporate ANR technology; however, designing them to function well usually entails many design tradeoffs, such as using larger ear nozzles that are uncomfortable to obtain desired noise reduction or that require added structures to hold the earphones to a user ear. To avoid these tradeoffs, the present inventors devised, among other things, an exemplary ITE ANR earphone that places its error measurement microphone in the ear nozzle that connects the driver front acoustic volume to a user ear canal. This placement allows use of a narrower more comfortable ear nozzle without compromising noise reduction and without requiring added holding structures. Moreover, the narrower ear nozzle also lowers the likelihood that the ANR circuitry will become unstable and produce undesirable noise.