公开(公告)号：USRE47816E1

公开(公告)日：2020-01-14

申请号：US15869245

申请日：2018-01-12

Applicant: Conversant Intellectual Property Management Inc.

Inventor： Hyoung Seub Rhie

IPC: G11C16/00 ,  G11C16/26 ,  H01L29/792 ,  H01L27/115 ,  G11C16/04 ,  G11C16/14 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/11582 ,  H01L27/1157

Abstract: A three-dimensional integrated circuit non-volatile memory array includes a memory array of vertical channel NAND flash strings connected between a substrate source line and upper layer connection lines which each include n-type drain regions and p-type body line contact regions alternately disposed on each side of undoped or lightly doped string body regions so that each NAND flash string includes a vertical string body portion connected to a horizontal string body portion formed from the string body regions of the upper body connection lines.

公开(公告)号：US10468109B2

公开(公告)日：2019-11-05

申请号：US14933264

申请日：2015-11-05

Applicant: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.

Inventor： Chung-Zen Chen ,  Yang-Chieh Lin ,  Chung-Shan Kuo

IPC: G11C16/08 ,  G11C16/14 ,  G11C16/16 ,  G11C16/02 ,  G11C16/04

Abstract: A memory device of the non-volatile type including a memory array having a plurality of memory cells organized as sectors, each sector having a main word line associated with a plurality of local word lines, each local word line coupled to the main word line by a respective local word line driver circuit, each of the local word line driver circuits consisting of a first MOS transistor coupled between the respective main word line and a respective local word line and a second MOS transistor coupled between the respective local word line and a first biasing terminal.

公开(公告)号：US20190303004A1

公开(公告)日：2019-10-03

申请号：US16387875

申请日：2019-04-18

Applicant: Conversant Intellectual Property Management Inc.

Inventor： Jin-Ki KIM

IPC: G06F3/06 ,  G06F12/02

Abstract: A method and system for controlling an MBC configured flash memory device to store data in an SBC storage mode, or a partial MBC storage mode. In a full MBC storage mode, pages of data are programmed sequentially from a first page to an Nth page for each physical row of memory cells. Up to N virtual page addresses per row of memory cells accompany each page to be programmed for designating the virtual position of the page in the row. For SBC or partial MBC data storage, a flash memory controller issues program command(s) to the MBC memory device using less than the maximum N virtual page addresses for each row. The MBC memory device sequentially executes programming operations up to the last received virtual page address for the row.

公开(公告)号：US20190189225A1

公开(公告)日：2019-06-20

申请号：US16221824

申请日：2018-12-17

Applicant: Conversant Intellectual Property Management Inc.

Inventor： Jin-Ki KIM ,  Peter B. GILLINGHAM

IPC: G11C16/30 ,  G11C5/14 ,  G11C16/14 ,  G11C16/12 ,  G11C16/10 ,  G11C16/26

CPC classification number: G11C16/30 ,  G11C5/14 ,  G11C5/143 ,  G11C5/145 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26

Abstract: A memory device includes core memory such as flash memory for storing data. The memory device includes a first power input to receive a first voltage used to power the flash memory. Additionally, the memory device includes a second power input to receive a second voltage. The memory device includes power management circuitry configured to receive the second voltage and derive one or more internal voltages. The power management circuitry supplies or conveys the internal voltages to the flash memory. The different internal voltages generated by the power management circuitry (e.g., voltage converter circuit) and supplied to the core memory enable operations such as read/program/erase with respect to cells in the core memory.

公开(公告)号：US20190173453A1

公开(公告)日：2019-06-06

申请号：US16226917

申请日：2018-12-20

Applicant: Conversant Intellectual Property Management Inc.

Inventor： Barry Alan HOBERMAN ,  Daniel L. HILLMAN ,  Jon Shiell

IPC: H03K3/012 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  H02J4/00

CPC classification number: H03K3/012 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  H01L2924/00 ,  H01L2924/0002 ,  H02J4/00 ,  Y02D10/126 ,  Y02D10/172 ,  Y02D50/20 ,  Y10T307/406 ,  Y10T307/414

Abstract: Systems and methods manage power in an integrated circuit using power islands. The integrated circuit includes a plurality of power islands wherein a power consumption of each power island within the plurality of power islands is independently controlled within each of the power islands. A power manager determines a target power level for one power island of the plurality of power islands. The power manager then determines an action to change a consumption power level of the one power island of the plurality of power islands to the target power level. The power manager performs the action to change the consumption power level of the one power island of the plurality of power islands to the target power level.

公开(公告)号：US09977731B2

公开(公告)日：2018-05-22

申请号：US14027858

申请日：2013-09-16

Applicant: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.

Inventor： Hong Beom Pyeon ,  Jin-Ki Kim ,  Peter B. Gillingham

IPC: G06F13/00 ,  G06F12/02 ,  G11C7/10 ,  G06F13/36 ,  G06F13/42 ,  G06F12/04 ,  G06F3/06 ,  G06F12/06

CPC classification number: G06F12/0238 ,  G06F3/0634 ,  G06F12/04 ,  G06F12/0646 ,  G06F13/36 ,  G06F13/4234 ,  G06F13/4291 ,  G11C7/10 ,  G11C7/1006 ,  G11C7/1018 ,  G11C7/1039 ,  G11C7/106 ,  G11C7/1087

Abstract: A composite memory device including discrete memory devices and a bridge device for controlling the discrete memory devices. The bridge device has memory organized as banks, where each bank is configured to have a virtual page size that is less than the maximum physical size of the page buffer. Therefore only a segment of data corresponding to the virtual page size stored in the page buffer is transferred to the bank. The virtual page size of the banks is provided in a virtual page size (VPS) configuration command having an ordered structure where the position of VPS data fields containing VPS configuration codes in the command correspond to different banks which are ordered from a least significant bank to a most significant bank. The VPS configuration command is variable in size, and includes only the VPS configuration codes for the highest significant bank being configured and the lower significant banks.

公开(公告)号：US09966133B2

公开(公告)日：2018-05-08

申请号：US15692206

申请日：2017-08-31

Applicant: Conversant Intellectual Property Management Inc.

Inventor： HakJune Oh ,  Hong Beom Pyeon ,  Jin-Ki Kim

IPC: G11C7/00 ,  G11C11/56 ,  G11C16/34 ,  G11C16/16 ,  G06F1/12 ,  G11C7/10 ,  G11C16/10 ,  G11C16/26 ,  G11C16/06

CPC classification number: G11C11/5628 ,  G06F1/12 ,  G11C7/1021 ,  G11C7/1051 ,  G11C7/1078 ,  G11C11/5642 ,  G11C16/06 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3445 ,  G11C2207/107

Abstract: An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.

公开(公告)号：USRE46819E1

公开(公告)日：2018-05-01

申请号：US14141686

申请日：2013-12-27

Applicant: Conversant Intellectual Property Management Inc.

Inventor： Peter Gillingham ,  Robert McKenzie

IPC: G06F13/42 ,  G11C29/50 ,  G11C7/10

CPC classification number: G06F13/4243 ,  G11C7/1066 ,  G11C29/50012 ,  G11C2207/2254

Abstract: A method of snap-shot data training to determine the optimum timing of the DQS enable signal in a single read operation is provided. This is accomplished by first writing a Gray code count sequence into the memory and then reading it back in a single burst. The controller samples the read burst at a fixed interval from the time the command was issued to determine the loop-around delay. A simple truth table lookup determines the optimum DQS enable timing for normal reads. Advantageously, during normal read operations, the first positive edge of the enabled DQS signal is used to sample a counter that is enabled every time a command is issued. If the counter sample changes, indicating timing drift has occurred, the DQS enable signal can be adjusted to compensate for the drift and maintain a position centered in the DQS preamble. This technique can also be applied to a system that uses the iterative approach to determining DQS enable timing on power up. Another embodiment of the invention is a simple, low latency clock domain crossing circuit based on the DQS latched sample of the counter.

公开(公告)号：US09935110B2

公开(公告)日：2018-04-03

申请号：US15410031

申请日：2017-01-19

Applicant: Conversant Intellectual Property Management Inc.

Inventor： Hyoung Seub Rhie

IPC: H01L27/108 ,  H01L49/02

CPC classification number: H01L27/10855 ,  H01L27/108 ,  H01L27/10814 ,  H01L27/10817 ,  H01L27/10873 ,  H01L28/90 ,  H01L28/91

Abstract: A high capacitance embedded capacitor and associated fabrication processes are disclosed for fabricating a capacitor stack in a multi-layer stack to include a first capacitor plate conductor formed with a cylinder-shaped storage node electrode formed in the multi-layer stack, a capacitor dielectric layer surrounding the cylinder-shaped storage node electrode, and a second capacitor plate conductor formed from a conductive layer in the multi-layer stack that is sandwiched between a bottom and top dielectric layer, where the cylinder-shaped storage node electrode is surrounded by and extends through the conductive layer.

公开(公告)号：US09899096B2

公开(公告)日：2018-02-20

申请号：US15411138

申请日：2017-01-20

Applicant: Conversant Intellectual Property Management Inc.

Inventor： Jin-Ki Kim

IPC: G11C11/34 ,  G11C16/34 ,  G11C16/04 ,  G11C16/16 ,  G11C16/26

CPC classification number: G11C16/3427 ,  G11C16/0483 ,  G11C16/16 ,  G11C16/26 ,  H01L27/11521 ,  H01L27/11524

Abstract: A NAND flash memory bank having a plurality of bitlines of a memory array connected to a page buffer, where NAND cell strings connected to the same bitline are formed in at least two well sectors. At least one well sector can be selectively coupled to an erase voltage during an erase operation, such that unselected well sectors are inhibited from receiving the erase voltage. When the area of the well sectors decrease, a corresponding decrease in the capacitance of each well sector results. Accordingly, higher speed erasing of the NAND flash memory cells relative to a single well memory bank is obtained when the charge pump circuit drive capacity remains unchanged. Alternately, a constant erase speed corresponding to a single well memory bank is obtained by matching a well segment having a specific area to a charge pump with reduced drive capacity. A reduced drive capacity charge pump will occupy less semiconductor chip area, thereby reducing cost.