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    Non-volatile semiconductor memory having multiple external power supplies
    3.
    发明授权
    Non-volatile semiconductor memory having multiple external power supplies 有权
    具有多个外部电源的非易失性半导体存储器

    公开(公告)号：US09576675B2

    公开(公告)日：2017-02-21

    申请号：US14969351

    申请日：2015-12-15

    Applicant: Conversant Intellectual Property Management Inc.

    Inventor： Jin-Ki Kim ,  Peter B. Gillingham

    IPC: G11C16/06 ,  G11C16/30 ,  G11C5/14 ,  G11C16/10 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  G11C16/04 ,  G11C16/08

    CPC classification number: G11C16/30 ,  G11C5/14 ,  G11C5/143 ,  G11C5/145 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26

    Abstract: A memory device includes core memory such as flash memory for storing data. The memory device includes a first power input to receive a first voltage used to power the flash memory. Additionally, the memory device includes a second power input to receive a second voltage. The memory device includes power management circuitry configured to receive the second voltage and derive one or more internal voltages. The power management circuitry supplies or conveys the internal voltages to the flash memory. The different internal voltages generated by the power management circuitry (e.g., voltage converter circuit) and supplied to the core memory enable operations such as read/program/erase with respect to cells in the core memory.

    Abstract translation: 存储器件包括诸如用于存储数据的闪存的核心存储器。 存储器件包括用于接收用于为闪速存储器供电的第一电压的第一电源输入。 另外，存储器件包括用于接收第二电压的第二电源输入。 存储器件包括被配置为接收第二电压并导出一个或多个内部电压的电源管理电路。 电源管理电路将内部电压提供或传送到闪存。 由功率管理电路（例如，电压转换器电路）产生并提供给核心存储器的不同的内部电压使得诸如针对核心存储器中的单元的读取/编程/擦除的操作。

    Clock mode determination in a memory system
    4.
    发明授权
    Clock mode determination in a memory system 有权
    存储器系统中的时钟模式确定

    公开(公告)号：US09552889B2

    公开(公告)日：2017-01-24

    申请号：US15183162

    申请日：2016-06-15

    Applicant: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.

    Inventor： Peter B. Gillingham ,  Graham Allan

    IPC: G11C8/00 ,  G11C16/32 ,  G11C16/04 ,  G11C16/10

    CPC classification number: G06F3/061 ,  G06F3/0655 ,  G06F3/0688 ,  G06F13/1694 ,  G11C7/1045 ,  G11C7/1078 ,  G11C7/1093 ,  G11C7/22 ,  G11C14/0018 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/28 ,  G11C16/32 ,  H03K2005/00247 ,  Y02D10/14

    Abstract: A clock mode configuration circuit for a memory device is described. A memory system includes any number of memory devices serially connected to each other, where each memory device receives a clock signal. The clock signal can be provided either in parallel to all the memory devices or serially from memory device to memory device through a common clock input. The clock mode configuration circuit in each memory device is set to a parallel mode for receiving the parallel clock signal, and to a serial mode for receiving a source synchronous clock signal from a prior memory device. Depending on the set operating mode, the data input circuits will be configured for the corresponding data signal format, and the corresponding clock input circuits will be either enabled or disabled. The parallel mode and the serial mode is set by sensing a voltage level of a reference voltage provided to each memory device.

    Abstract translation: 描述了用于存储器件的时钟模式配置电路。 存储器系统包括彼此串行连接的任何数量的存储器件，其中每个存储器件接收时钟信号。 可以将时钟信号并行地提供给所有存储器件，或者通过公共时钟输入从存储器件到存储器器件串行提供。 每个存储器件中的时钟模式配置电路被设置为用于接收并行时钟信号的并行模式，以及用于从现有存储器件接收源同步时钟信号的串行模式。 根据设置的工作模式，数据输入电路将被配置为相应的数据信号格式，相应的时钟输入电路将被启用或禁用。 通过感测提供给每个存储器件的参考电压的电压电平来设置并联模式和串行模式。

    Clock mode determination in a memory system
    5.
    发明授权
    Clock mode determination in a memory system 有权
    存储器系统中的时钟模式确定

    公开(公告)号：US09042199B2

    公开(公告)日：2015-05-26

    申请号：US14491440

    申请日：2014-09-19

    Applicant: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.

    Inventor： Peter B. Gillingham ,  Graham Allan

    IPC: G11C8/00 ,  G11C16/10

    CPC classification number: G06F3/061 ,  G06F3/0655 ,  G06F3/0688 ,  G06F13/1694 ,  G11C7/1045 ,  G11C7/1078 ,  G11C7/1093 ,  G11C7/22 ,  G11C14/0018 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/28 ,  G11C16/32 ,  H03K2005/00247 ,  Y02D10/14

    Abstract: A clock mode configuration circuit for a memory device is described. A memory system includes any number of memory devices serially connected to each other, where each memory device receives a clock signal. The clock signal can be provided either in parallel to all the memory devices or serially from memory device to memory device through a common clock input. The clock mode configuration circuit in each memory device is set to a parallel mode for receiving the parallel clock signal, and to a serial mode for receiving a source synchronous clock signal from a prior memory device. Depending on the set operating mode, the data input circuits will be configured for the corresponding data signal format, and the corresponding clock input circuits will be either enabled or disabled. The parallel mode and the serial mode is set by sensing a voltage level of a reference voltage provided to each memory device.

    Abstract translation: 描述了用于存储器件的时钟模式配置电路。 存储器系统包括彼此串行连接的任何数量的存储器件，其中每个存储器件接收时钟信号。 可以将时钟信号并行地提供给所有存储器件，或者通过公共时钟输入从存储器件到存储器器件串行提供。 每个存储器件中的时钟模式配置电路被设置为用于接收并行时钟信号的并行模式，以及用于从现有存储器件接收源同步时钟信号的串行模式。 根据设置的工作模式，数据输入电路将被配置为相应的数据信号格式，相应的时钟输入电路将被启用或禁用。 通过感测提供给每个存储器件的参考电压的电压电平来设置并联模式和串行模式。

    Clock mode determination in a memory system
    6.
    发明授权
    Clock mode determination in a memory system 有权

    公开(公告)号：US10140028B2

    公开(公告)日：2018-11-27

    申请号：US15957120

    申请日：2018-04-19

    Applicant: Conversant Intellectual Property Management Inc.

    Inventor： Peter B. Gillingham ,  Graham Allan

    IPC: G11C8/00 ,  G06F3/06 ,  G11C7/22 ,  G11C7/10 ,  G11C14/00 ,  G06F13/16 ,  G11C16/04 ,  G11C16/32 ,  G11C16/28 ,  G11C16/10 ,  H03K5/00

    Abstract: A clock mode configuration circuit for a memory device is described. A memory system includes any number of memory devices serially connected to each other, where each memory device receives a clock signal. The clock signal can be provided either in parallel to all the memory devices or serially from memory device to memory device through a common clock input. The clock mode configuration circuit in each memory device is set to a parallel mode for receiving the parallel clock signal, and to a serial mode for receiving a source synchronous clock signal from a prior memory device. Depending on the set operating mode, the data input circuits will be configured for the corresponding data signal format, and the corresponding clock input circuits will be either enabled or disabled. The parallel mode and the serial mode is set by sensing a voltage level of a reference voltage provided to each memory device.

    CLOCK MODE DETERMINATION IN A MEMORY SYSTEM
    7.
    发明申请
    CLOCK MODE DETERMINATION IN A MEMORY SYSTEM 有权

    公开(公告)号：US20210132799A1

    公开(公告)日：2021-05-06

    申请号：US16950204

    申请日：2020-11-17

    Applicant: Conversant Intellectual Property Management Inc.

    Inventor： Peter B. Gillingham ,  Graham Allan

    IPC: G06F3/06 ,  G06F13/16 ,  G11C7/10 ,  G11C7/22 ,  G11C16/10 ,  G11C16/28 ,  G11C16/32 ,  G11C16/04 ,  G11C14/00

    Abstract: A clock mode configuration circuit for a memory device is described. A memory system includes any number of memory devices serially connected to each other, where each memory device receives a clock signal. The clock signal can be provided either in parallel to all the memory devices or serially from memory device to memory device through a common clock input. The clock mode configuration circuit in each memory device is set to a parallel mode for receiving the parallel clock signal, and to a serial mode for receiving a source synchronous clock signal from a prior memory device. Depending on the set operating mode, the data input circuits will be configured for the corresponding data signal format, and the corresponding clock input circuits will be either enabled or disabled. The parallel mode and the serial mode is set by sensing a voltage level of a reference voltage provided to each memory device.

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