公开(公告)号：US10796998B1

公开(公告)日：2020-10-06

申请号：US16380318

申请日：2019-04-10

Applicant: GaN Systems Inc.

Inventor： Thomas Macelwee

IPC: H01L29/78 ,  H01L23/532 ,  H01L29/20 ,  H01L29/778 ,  H01L29/16 ,  H01L29/739

Abstract: Embedded packaging for high voltage, high temperature operation of power semiconductor devices is disclosed, wherein a semiconductor die is embedded in a dielectric body comprising a dielectric polymer composition characterized by a conductivity transition temperature Tc, a first activation energy EaLow for conduction in a temperature range below Tc, and a second activation energy EaHigh for conduction in a temperature range above Tc. A test methodology is disclosed for selecting a dielectric epoxy composition having values of Tc, EaLow and EaHigh that provide a conduction value below a required reliability threshold, e.g. ≤5×10−13 S/cm, for a specified operating voltage and temperature. For example, the power semiconductor device comprises a GaN HEMT for operation at >100V wherein the package body is formed from a laminated dielectric epoxy composition for operation at >150 C, wherein Tc is ≥75 C, EaLow is ≤0.2 eV and EaHigh is ≤1 eV, for improved reliability for high voltage, high temperature operation.

公开(公告)号：US20200185508A1

公开(公告)日：2020-06-11

申请号：US16212755

申请日：2018-12-07

Applicant: GaN Systems Inc.

Inventor： Thomas MACELWEE

IPC: H01L29/66 ,  H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L21/308 ,  H01L21/02

Abstract: GaN HEMT device structures and methods of fabrication are provided. A masking layer forms a p-dopant diffusion barrier and selective growth of p-GaN in the gate region, using low temperature processing, reduces deleterious effects of out-diffusion of p-dopant into the 2DEG channel. A structured AlxGa1-xN barrier layer includes a first thickness having a first Al %, and a second thickness having a second Al %, greater than the first Al %. At least part of the second thickness of the AlxGa1-xN barrier layer in the gate region is removed, before selective growth of p-GaN in the gate region. The first Al % and first thickness are selected to determine the threshold voltage Vth and the second Al % and second thickness are selected to determine the Rdson and dynamic Rdson of the GaN HEMT, so that each may be separately determined to improve device performance, and provide a smaller input FOM (Figure of Merit).

公开(公告)号：US20200091291A1

公开(公告)日：2020-03-19

申请号：US16688008

申请日：2019-11-19

Applicant: GaN Systems Inc.

Inventor： Ahmad MIZAN ,  Hossein MOUSAVIAN ,  Xiaodong CUI

IPC: H01L29/06 ,  H01L29/205 ,  H01L23/522 ,  H01L23/528 ,  H01L23/482 ,  H01L29/423

Abstract: Circuit-Under-Pad (CUP) device topologies for high current lateral GaN power transistors comprise first and second levels of on-chip metallization M1 and M2; M1 defines source, drain and gate finger electrodes of a plurality of sections of a multi-section transistor and a gate bus; M2 defines an overlying contact structure comprising a drain pad and source pads extending over active regions of each section. The drain and source pads of M2 are interconnected by conductive micro-vias to respective underlying drain and source finger electrodes of M1. The pad structure and the micro-via interconnections are configured to reduce current density in self-supported widths of source and drain finger electrodes, i.e. to optimize a maximum current density for each section. For reduced gate loop inductance, part of each source pad is routed over the gate bus. Proposed CUP device structures provide for higher current carrying capability and reduced drain-source resistance.

公开(公告)号：US20190238062A1

公开(公告)日：2019-08-01

申请号：US16251696

申请日：2019-01-18

Applicant: GaN Systems Inc.

Inventor： Juncheng LU ,  Di CHEN ,  Larry SPAZIANI

IPC: H02M7/487 ,  H02M7/537 ,  H03K17/0412 ,  H03K17/12 ,  H03K17/284 ,  H03K17/60 ,  H03K17/687 ,  H01L29/739

Abstract: A 3-level T-type neutral point clamped (NPC) inverter/rectifier is disclosed in which neutral point clamping is dynamically enabled/disabled responsive to load, e.g. enabled at low load for operation in a first mode as a 3-level inverter/rectifier and disabled at high/peak load for operation in a second mode as a 2-level inverter/rectifier. When the neutral clamping leg is enabled only under low load and low current, middle switches S2 and S3 can be smaller, lower cost devices with a lower current rating. Si, SiC, GaN and hybrid implementations provide options to optimize efficiency for specific load ratios and applications. For reduced switching losses and enhanced performance of inverters based on Si-IGBT power switches, a hybrid implementation of the dual-mode T-type NPC inverter is proposed, wherein switches S1 and S4 comprise Si-IGBTs and switches S2 and S3 of the neutral clamping leg comprise GaN HEMTs. Applications include electric vehicle traction inverters.

公开(公告)号：US10249506B2

公开(公告)日：2019-04-02

申请号：US15712373

申请日：2017-09-22

Applicant: GaN Systems Inc.

Inventor： Thomas Macelwee ,  Greg P. Klowak ,  Howard Tweddle

IPC: H01L21/30 ,  H01L21/78 ,  H01L29/205 ,  H01L29/778 ,  H01L29/66 ,  H01L21/306 ,  H01L21/02 ,  H01L23/58 ,  H01L23/31 ,  H01L23/00 ,  C01B21/06 ,  H05B33/08 ,  C01G15/00 ,  H01L29/20

Abstract: A GaN-on-Si device structure and a method of fabrication are disclosed for improved die yield and device reliability of high current/high voltage lateral GaN transistors. A plurality of conventional GaN device structures comprising GaN epi-layers are fabricated on a silicon substrate (GaN-on-Si die). After processing of on-chip interconnect layers, a trench structure is defined around each die, through the GaN epi-layers and into the silicon substrate. A trench cladding is provided on proximal sidewalls, comprising at least one of a passivation layer and a conductive metal layer. The trench cladding extends over exposed surfaces of the GaN epi-layers, over the interface region with the substrate, and over the exposed surfaces of the interconnect layers. This structure reduces risk of propagation of dicing damage and defects or cracks in the GaN epi-layers into active device regions. A metal trench cladding acts as a barrier for electro-migration of mobile ions.

公开(公告)号：US09818692B2

公开(公告)日：2017-11-14

申请号：US15078023

申请日：2016-03-23

Applicant: GaN Systems Inc.

Inventor： John Roberts ,  Greg P. Klowak ,  Cameron McKnight-MacNeil

IPC: H01L23/528 ,  H01L21/66 ,  H01L27/095 ,  H01L29/40 ,  H01L29/778 ,  H01L23/373 ,  H01L29/20 ,  H01L29/06 ,  H01L23/36

CPC classification number: H01L23/528 ,  H01L22/32 ,  H01L23/36 ,  H01L23/3737 ,  H01L27/095 ,  H01L29/0619 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/7786

Abstract: Devices and systems comprising high current/high voltage GaN semiconductor devices are disclosed. A GaN die, comprising a lateral GaN transistor, is sandwiched between an overlying header and an underlying composite thermal dielectric layer. Fabrication comprises providing a conventional GaN device structure fabricated on a low cost silicon substrate (GaN-on-Si die), mechanically and electrically attaching source, drain and gate contact pads of the GaN-on-Si die to corresponding contact areas of conductive tracks of the header, then entirely removing the silicon substrate. The exposed substrate-surface of the epi-layer stack is coated with the composite dielectric thermal layer. Preferably, the header comprises a ceramic dielectric support layer having a CTE matched to the GaN epi-layer stack. The thermal dielectric layer comprises a high dielectric strength thermoplastic polymer and a dielectric filler having a high thermal conductivity. This structure offers improved electrical breakdown resistance and effective thermal dissipation compared to conventional GaN-on-Si device structures.

公开(公告)号：US09105560B2

公开(公告)日：2015-08-11

申请号：US14105569

申请日：2013-12-13

Applicant: GAN SYSTEMS INC.

Inventor： John Roberts ,  Greg Klowak

IPC: H01L25/18 ,  H01L23/495 ,  H01F19/08 ,  H01L23/64 ,  H01L23/00

CPC classification number: H03K17/687 ,  H01F19/08 ,  H01L23/49524 ,  H01L23/49548 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/645 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2224/0557 ,  H01L2224/06051 ,  H01L2224/06131 ,  H01L2224/06181 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/32245 ,  H01L2224/40245 ,  H01L2224/48137 ,  H01L2224/48195 ,  H01L2224/48247 ,  H01L2224/49107 ,  H01L2224/49175 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/12035 ,  H01L2924/1204 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/19104 ,  H01L2924/30107 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Devices and systems comprising driver circuits are disclosed for MOSFET driven, normally-on gallium nitride (GaN) power transistors. Preferably, a low power, high speed CMOS driver circuit with an integrated low voltage, lateral MOSFET driver is series coupled, in a hybrid cascode arrangement to a high voltage GaN HEMT, for improved control of noise and voltage transients. Co-packaging of a GaN transistor die and a CMOS driver die using island topology contacts, through substrate vias, and a flip-chip, stacked configuration provides interconnections with low inductance and resistance, and provides effective thermal management. Co-packaging of a CMOS input interface circuit with the CMOS driver and GaN transistor allows for a compact, integrated CMOS driver with enhanced functionality including shut-down and start-up conditioning for safer operation, particularly for high voltage and high current switching. Preferred embodiments also provide isolated, self-powered, high speed driver devices, with reduced input losses.

Abstract translation: 公开了包括驱动电路的器件和系统，用于MOSFET驱动的常规氮化镓（GaN）功率晶体管。 优选地，具有集成的低电压横向MOSFET驱动器的低功率高速CMOS驱动器电路以混合共源共栅布置串联耦合到高电压GaN HEMT，用于改善噪声和电压瞬变的控制。 使用岛拓扑触点，通过衬底通孔和倒装芯片堆叠配置来共同封装GaN晶体管管芯和CMOS驱动器管芯，提供低电感和电阻的互连，并提供有效的热管理。 CMOS输入接口电路与CMOS驱动器和GaN晶体管的共同封装允许具有增强功能的紧凑集成CMOS驱动器，包括关闭和启动调节，以实现更安全的操作，特别是对于高电压和高电流切换。 优选实施例还提供具有减小的输入损耗的隔离，自供电的高速驱动器件。

公开(公告)号：US20240393374A1

公开(公告)日：2024-11-28

申请号：US18322441

申请日：2023-05-23

Applicant: GAN SYSTEMS INC.

Inventor： Lucas Andrew MILNER ,  Marco A. ZUNIGA ,  Nan XING ,  Robert Wayne MOUNGER ,  Edward MACROBBIE ,  Sridhar RAMASWAMY ,  Ahmad MIZANNOJEHDEHI ,  Thomas William MACELWEE

IPC: G01R19/00

Abstract: A current sense circuit that allows for accurate sensing of a power current that flows through a power transistor as the power transistor ages. The circuit includes the power transistor, a sense transistor and a pull-up component. The control nodes of the power transistor and the sense transistor are connected, causing the power transistor and sense transistor to be on or off simultaneously. The pull-up component is connected between the input node of the power transistor and the input node of the sense transistor. When power is provided to the pull-up component, and when each of the power transistor and sense transistor are off, the pull-up component forces a voltage present at the sense transistor input node to be approximately equal to a voltage present at the power transistor input node, causing the sense and power transistors to age together.

公开(公告)号：US12027449B2

公开(公告)日：2024-07-02

申请号：US17974794

申请日：2022-10-27

Applicant: GaN Systems Inc.

Inventor： Hossein Mousavian ,  Edward Macrobbie

IPC: H01L29/417 ,  H01L23/482 ,  H01L29/20 ,  H01L29/778 ,  H01L29/861

CPC classification number: H01L23/4824 ,  H01L29/2003 ,  H01L29/41758 ,  H01L29/7786 ,  H01L29/8611

Abstract: A lateral power semiconductor device structure comprises a pad-over-active topology wherein on-chip interconnect metallization and contact pad placement is optimized to reduce interconnect resistance. For a lateral GaN HEMT, wherein drain, source and gate finger electrodes extend between first and second edges of an active region, the source and drain buses run across the active region at positions intermediate the first and second edges of the active region, interconnecting first and second portions of the source fingers and drain fingers which extend laterally towards the first and second edges of the active region. External contact pads are placed on the source and drain buses. For a given die size, this interconnect structure reduces lengths of current paths in the source and drain metal interconnect, and provides, for example, at least one of lower interconnect resistance, increased current capability per unit active area, and increased active area usage per die.

公开(公告)号：US11909384B2

公开(公告)日：2024-02-20

申请号：US17741813

申请日：2022-05-11

Applicant: GaN Systems Inc.

Inventor： Di Chen

IPC: H02H3/24 ,  H03K17/08 ,  H03K17/22 ,  H02M1/36 ,  H03K17/687 ,  H03K17/0814

CPC classification number: H03K17/223 ,  H02H3/243 ,  H02M1/36 ,  H03K17/08142 ,  H03K17/687

Abstract: A protected direct-drive depletion-mode (D-mode) GaN semiconductor half-bridge power module is disclosed. Applications include high power inverter applications, such as 100 kW to 200 kW electric vehicle traction inverters, and other motor drives. The high-side switch is a normally-on D-mode GaN semiconductor power switch Q1 in series with a normally-off LV Si MOSFET power switch M1 and the low-side switch is a normally on D-mode GaN semiconductor power switch Q2. The gates of both Q1 and Q2 are directly driven. M1 in series with Q1 provides a high-side switch which is a normally-off device for start-up and fail-safe protection. M1 may also be used for current sensing and overcurrent protection. For example, a control circuit determines an operational mode of M1 responsive to a UVLO signal and a voltage sense signal indicative of an overcurrent event. Examples of single phase and three-phase half-bridge modules and driver circuits are described.