公开(公告)号：US20220005999A1

公开(公告)日：2022-01-06

申请号：US16918708

申请日：2020-07-01

申请人： Christian Lavoie ,  Benjamin Wymore ,  Markus Brink ,  Stephen L. Brown

发明人： Christian Lavoie ,  Benjamin Wymore ,  Markus Brink ,  Stephen L. Brown

IPC分类号： H01L39/12 ,  H01L39/24 ,  G06N10/00

摘要： Techniques facilitating formation of amorphous superconducting alloys for superconducting circuits are provided. A device can comprise one or more superconducting components that comprise an amorphous superconducting alloy comprising two or more elements. At least one element of the two or more elements is a superconducting element.

公开(公告)号：US10396229B2

公开(公告)日：2019-08-27

申请号：US13103583

申请日：2011-05-09

申请人： Joel P. De Souza ,  Harold J. Hovel ,  Daniel A. Inns ,  Jeehwan Kim ,  Christian Lavoie ,  Devendra K. Sadana ,  Katherine L. Saenger ,  Davood Shahrjerdi ,  Zhen Zhang

发明人： Joel P. De Souza ,  Harold J. Hovel ,  Daniel A. Inns ,  Jeehwan Kim ,  Christian Lavoie ,  Devendra K. Sadana ,  Katherine L. Saenger ,  Davood Shahrjerdi ,  Zhen Zhang

IPC分类号： H01L31/07 ,  H01L31/0224 ,  H01L31/18 ,  H01L31/068

摘要： A solar cell having n-type and p-type interdigitated back contacts (IBCs), which cover the entire back surface of the absorber layer. The spatial separation of the IBCs is in a direction perpendicular to the back surface, thus providing borderless contacts having a zero-footprint separation. As the contacts are on the back, photons incident on the cell's front surface can be absorbed without any shadowing.

公开(公告)号：US09006801B2

公开(公告)日：2015-04-14

申请号：US13013081

申请日：2011-01-25

申请人： Christian Lavoie ,  Zhengwen Li ,  Ahmet S. Ozcan ,  Filippos Papadatos ,  Chengwen Pei ,  Jian Yu

发明人： Christian Lavoie ,  Zhengwen Li ,  Ahmet S. Ozcan ,  Filippos Papadatos ,  Chengwen Pei ,  Jian Yu

IPC分类号： H01L21/285 ,  H01L21/336 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/311 ,  H01L21/768

CPC分类号： H01L29/7833 ,  H01L21/0217 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/28518 ,  H01L21/31116 ,  H01L21/32053 ,  H01L21/321 ,  H01L21/32133 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76829 ,  H01L23/535 ,  H01L29/1054 ,  H01L29/45 ,  H01L29/456 ,  H01L29/458 ,  H01L29/4975 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7843 ,  H01L29/7845 ,  H01L29/7849

摘要： A method of forming a semiconductor device is provided that includes forming a first metal semiconductor alloy on a semiconductor containing surface, forming a dielectric layer over the first metal semiconductor alloy, forming an opening in the dielectric layer to provide an exposed surface the first metal semiconductor alloy, and forming a second metal semiconductor alloy on the exposed surface of the first metal semiconductor alloy. In another embodiment, the method includes forming a gate structure on a channel region of a semiconductor substrate, forming a dielectric layer over at least a source region and a drain region, forming an opening in the dielectric layer to provide an exposed surface the semiconductor substrate, forming a first metal semiconductor alloy on the exposed surface of the semiconductor substrate, and forming a second metal semiconductor alloy on the first metal semiconductor alloy.

摘要翻译： 提供一种形成半导体器件的方法，包括在半导体容纳表面上形成第一金属半导体合金，在第一金属半导体合金上形成电介质层，在电介质层中形成开口以提供第一金属半导体 合金，并且在第一金属半导体合金的暴露表面上形成第二金属半导体合金。 在另一个实施例中，该方法包括在半导体衬底的沟道区上形成栅极结构，在至少源极区和漏极区上形成电介质层，在电介质层中形成开口以提供暴露表面，半导体衬底 在所述半导体衬底的暴露表面上形成第一金属半导体合金，并在所述第一金属半导体合金上形成第二金属半导体合金。

公开(公告)号：US08981565B2

公开(公告)日：2015-03-17

申请号：US13428184

申请日：2012-03-23

申请人： Christian Lavoie ,  Dong-Ick Lee ,  Ahmet Serkan Ozcan ,  Zhen Zhang

发明人： Christian Lavoie ,  Dong-Ick Lee ,  Ahmet Serkan Ozcan ,  Zhen Zhang

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/285 ,  H01L29/66

CPC分类号： H01L29/665 ,  H01L21/02381 ,  H01L21/02631 ,  H01L21/244 ,  H01L21/28518 ,  H01L21/32133 ,  H01L21/324 ,  H01L29/161

摘要： In one aspect, a method of fabricating a metal silicide includes the following steps. A semiconductor material selected from the group consisting of silicon and silicon germanium is provided. A metal(s) is deposited on the semiconductor material. A first anneal is performed at a temperature and for a duration sufficient to react the metal(s) with the semiconductor material to form an amorphous layer including an alloy formed from the metal(s) and the semiconductor material, wherein the temperature at which the first anneal is performed is below a temperature at which a crystalline phase of the alloy is formed. An etch is used to selectively remove unreacted portions of the metal(s). A second anneal is performed at a temperature and for a duration sufficient to crystallize the alloy thus forming the metal silicide. A device contact and a method of fabricating a FET device are also provided.

摘要翻译： 一方面，制造金属硅化物的方法包括以下步骤。 提供从由硅和硅锗组成的组中选择的半导体材料。 一种或多种金属沉积在半导体材料上。 在足以使金属与半导体材料反应的温度和持续时间进行第一退火以形成包括由金属和半导体材料形成的合金的非晶层，其中， 进行第一退火低于形成合金的结晶相的温度。 使用蚀刻来选择性地去除金属的未反应部分。 在足以使合金结晶形成金属硅化物的温度和持续时间内进行第二次退火。 还提供了器件触点和制造FET器件的方法。

公开(公告)号：US20130069124A1

公开(公告)日：2013-03-21

申请号：US13237732

申请日：2011-09-20

申请人： Bin Yang ,  Christian Lavoie ,  Emre Alptekin ,  Ahmet S. Ozcan ,  Cung D. Tran ,  Mark Raymond

发明人： Bin Yang ,  Christian Lavoie ,  Emre Alptekin ,  Ahmet S. Ozcan ,  Cung D. Tran ,  Mark Raymond

IPC分类号： H01L29/78 ,  H01L21/20

CPC分类号： H01L29/665 ,  H01L21/28518 ,  H01L29/6659 ,  H01L29/7833

摘要： An MOSFET device having a Silicide layer of uniform thickness, and methods for its fabrication, are provided. One such method involves depositing a metal layer over wide and narrow contact trenches on the surface of a silicon semiconductor substrate. Upon formation of a uniformly thin amorphous intermixed alloy layer at the metal/silicon interface, the excess (unreacted) metal is removed. The device is annealed to facilitate the formation of a thin silicide layer on the substrate surface which exhibits uniform thickness at the bottoms of both wide and narrow contact trenches.

摘要翻译： 提供具有均匀厚度的硅化物层的MOSFET器件及其制造方法。 一种这样的方法包括在硅半导体衬底的表面上的宽且窄的接触沟槽上沉积金属层。 在金属/硅界面处形成均匀薄的无定形混合合金层时，除去过量的（未反应的）金属。 该器件被退火以促进在衬底表面上形成薄的硅化物层，其在宽和窄接触沟槽的底部显示均匀的厚度。

公开(公告)号：US08349716B2

公开(公告)日：2013-01-08

申请号：US12911186

申请日：2010-10-25

申请人： Ming Cai ,  Christian Lavoie ,  Ahmet S. Ozcan ,  Bin Yang ,  Zhen Zhang

发明人： Ming Cai ,  Christian Lavoie ,  Ahmet S. Ozcan ,  Bin Yang ,  Zhen Zhang

IPC分类号： H01L21/336 ,  H01L21/04

CPC分类号： H01L21/2257 ,  H01L21/28512 ,  H01L21/28518 ,  H01L29/665 ,  H01L29/66643

摘要： Disclosed is a semiconductor device having a p-n junction with reduced junction leakage in the presence of metal silicide defects that extend to the junction and a method of forming the device. Specifically, a semiconductor layer having a p-n junction is formed. A metal silicide layer is formed on the semiconductor layer and a dopant is implanted into the metal silicide layer. An anneal process is performed causing the dopant to migrate toward the metal silicide-semiconductor layer interface such that the peak concentration of the dopant will be within a portion of the metal silicide layer bordering the metal silicide-semiconductor layer interface and encompassing the defects. As a result, the silicide to silicon contact is effectively engineered to increase the Schottky barrier height at the defect, which in turn drastically reduces any leakage that would otherwise occur, when the p-n junction is in reverse polarity.

摘要翻译： 公开了一种具有p-n结的半导体器件，其在存在延伸到结的金属硅化物缺陷的情况下具有减少的结漏电以及形成器件的方法。 具体地说，形成具有p-n结的半导体层。 在半导体层上形成金属硅化物层，并且将掺杂剂注入到金属硅化物层中。 执行退火处理，使掺杂剂朝向金属硅化物半导体层界面迁移，使得掺杂剂的峰值浓度将在金属硅化物层的与金属硅化物半导体层界面接壤并包围缺陷的部分内。 结果，硅化物与硅接触被有效地设计以增加缺陷处的肖特基势垒高度，这反过来大大降低了当p-n结处于相反极性时将会发生的任何泄漏。

公开(公告)号：US20120299104A1

公开(公告)日：2012-11-29

申请号：US13571429

申请日：2012-08-10

申请人： Jin Cai ,  Dechao Guo ,  Marwan H. Khater ,  Christian Lavoie ,  Zhen Zhang

发明人： Jin Cai ,  Dechao Guo ,  Marwan H. Khater ,  Christian Lavoie ,  Zhen Zhang

IPC分类号： H01L29/78

CPC分类号： H01L29/66772 ,  H01L29/458 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66621

摘要： A field effect transistor (FET) includes a semiconductor on insulator substrate, the substrate comprising a top semiconductor layer; source and drain regions located in the top semiconductor layer; a channel region located in the top semiconductor layer between the source region and the drain region, the channel region having a thickness that is less than a thickness of the source and drain regions; a gate located over the channel region; and a supporting material located over the source and drain regions adjacent to the gate.

摘要翻译： 场效应晶体管（FET）包括绝缘体上半导体衬底，所述衬底包括顶部半导体层; 源极和漏极区域位于顶部半导体层中; 位于源极区域和漏极区域之间的顶部半导体层中的沟道区域，沟道区域的厚度小于源极和漏极区域的厚度; 位于通道区域上方的门; 以及位于与栅极相邻的源极和漏极区域之上的支撑材料。

公开(公告)号：US20120298965A1

公开(公告)日：2012-11-29

申请号：US13568839

申请日：2012-08-07

申请人： Wilfried Haensch ,  Christian Lavoie ,  Christine Qiqing Ouyang ,  Xiaoyan Shao ,  Paul M. Solomon ,  Zhen Zhang ,  Bin Yang

发明人： Wilfried Haensch ,  Christian Lavoie ,  Christine Qiqing Ouyang ,  Xiaoyan Shao ,  Paul M. Solomon ,  Zhen Zhang ,  Bin Yang

IPC分类号： H01L29/772 ,  B82Y99/00

CPC分类号： H01L29/0673 ,  H01L21/823814 ,  H01L29/41791

摘要： A multigate structure which comprises a semiconductor substrate; an ultra-thin silicon or carbon bodies of less than 20 nanometers thick located on the substrate; an electrolessly deposited metallic layer selectively located on the side surfaces and top surfaces of the ultra-thin silicon or carbon bodies and selectively located on top of the multigate structures to make electrical contact with the ultra-thin silicon or carbon bodies and to minimize parasitic resistance, and wherein the ultra-thin silicon or carbon bodies and metallic layer located thereon form source and drain regions is provided along with a process to fabricate the structure.

摘要翻译： 一种多栅格结构，包括半导体衬底; 位于基板上的小于20纳米厚的超薄硅或碳体; 选择性地位于超薄硅或碳体的侧表面和顶表面上的无电沉积金属层，并且选择性地位于多结构结构的顶部上以与超薄硅或碳体电接触并最小化寄生电阻 并且其中位于其上的超薄硅或碳体和金属层形成源区和漏区以及制造该结构的工艺。

公开(公告)号：US20120285518A1

公开(公告)日：2012-11-15

申请号：US13103583

申请日：2011-05-09

申请人： Joel P. De Souza ,  Harold John Hovel ,  Daniel Inns ,  Jeehwan Kim ,  Christian Lavoie ,  Devendra K. Sadana ,  Katherine L. Saenger ,  Davood Shahrjerdi ,  Zhen Zhang

发明人： Joel P. De Souza ,  Harold John Hovel ,  Daniel Inns ,  Jeehwan Kim ,  Christian Lavoie ,  Devendra K. Sadana ,  Katherine L. Saenger ,  Davood Shahrjerdi ,  Zhen Zhang

IPC分类号： H01L31/06 ,  H01L31/18

CPC分类号： H01L31/0682 ,  H01L31/022441 ,  H01L31/07 ,  H01L31/1804 ,  H01L31/1864 ,  Y02E10/547 ,  Y02P70/521

摘要： A solar cell having n-type and p-type interdigitated back contacts (IBCs), which cover the entire back surface of the absorber layer. The spatial separation of the IBCs is in a direction perpendicular to the back surface, thus providing borderless contacts having a zero-footprint separation. As the contacts are on the back, photons incident on the cell's front surface can be absorbed without any shadowing.

摘要翻译： 一种太阳能电池，其具有覆盖吸收层的整个后表面的n型和p型交叉指接头（IBC）。 IBC的空间分离是在垂直于后表面的方向上，从而提供具有零占位分隔的无边界接触。 随着触点在背面，入射在电池前表面的光子可以被吸收而不会有任何阴影。

公开(公告)号：US20120202345A1

公开(公告)日：2012-08-09

申请号：US13022474

申请日：2011-02-07

申请人： Benjamin Luke Fletcher ,  Christian Lavoie ,  Siegfried Lutz Maurer ,  Zhen Zhang

发明人： Benjamin Luke Fletcher ,  Christian Lavoie ,  Siegfried Lutz Maurer ,  Zhen Zhang

IPC分类号： H01L21/3205 ,  B82Y40/00

CPC分类号： B82Y40/00 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/16 ,  H01L29/66469 ,  H01L29/775

摘要： Techniques for silicide, germanide or germanosilicide formation in extremely small structures are provided. In one aspect, a method for forming a silicide, germanide or germanosilicide in a three-dimensional silicon, germanium or silicon germanium structure having extremely small dimensions is provided. The method includes the following steps. At least one element is implanted into the structure. At least one metal is deposited onto the structure. The structure is annealed to intersperse the metal within the silicon, germanium or silicon germanium to form the silicide, germanide or germanosilicide wherein the implanted element serves to prevent morphological degradation of the silicide, germanide or germanosilicide. The implanted element can include at least one of carbon, fluorine and silicon.

摘要翻译： 提供了极小结构中硅化物，锗化锗或锗硅化物形成技术。 一方面，提供了在具有极小尺寸的三维硅，锗或硅锗结构中形成硅化物，锗化锗或锗硅化物的方法。 该方法包括以下步骤。 将至少一个元件植入结构中。 至少一种金属沉积在结构上。 将该结构退火以将硅，锗或硅锗内的金属分散以形成硅化物，锗化锗或锗硅化物，其中所述植入元件用于防止硅化物，锗化物或锗硅化物的形态降解。 植入元件可以包括碳，氟和硅中的至少一种。