公开(公告)号：US4911859A

公开(公告)日：1990-03-27

申请号：US244735

申请日：1988-09-15

申请人： Charles J. Bunczk ,  Peter A. Burke ,  William R. Camp

发明人： Charles J. Bunczk ,  Peter A. Burke ,  William R. Camp

IPC分类号： A01N59/12 ,  C11D1/22 ,  C11D3/22 ,  C11D3/37 ,  C11D3/48 ,  C11D17/00

CPC分类号： C11D3/485 ,  A01N59/12 ,  C11D17/0056 ,  C11D3/225 ,  C11D3/3707 ,  C11D1/22

摘要： Solid cake lavoratory cleansing block composition comprising an iodophor, polyethylene oxide polymer having a molecular weight between about 1 to 6 million, a dye, calcium sulfate and optional ingredients which include fragrances, binders, filler material and mixtures thereof.

公开(公告)号：US08889532B2

公开(公告)日：2014-11-18

申请号：US13170033

申请日：2011-06-27

申请人： Peter A. Burke ,  Gordon M. Grivna ,  Balaji Padmanabhan ,  Prasad Venkatraman

发明人： Peter A. Burke ,  Gordon M. Grivna ,  Balaji Padmanabhan ,  Prasad Venkatraman

IPC分类号： H01L21/36 ,  H01L21/20 ,  H01L21/336 ,  H01L29/66 ,  H01L29/40 ,  H01L29/78 ,  H01L29/739 ,  H01L29/08 ,  H01L29/45 ,  H01L29/417 ,  H01L29/49 ,  H01L29/423

CPC分类号： H01L29/7813 ,  H01L29/0869 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66348 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/7827

摘要： In one embodiment, a vertical insulated-gate field effect transistor includes a shield electrode formed in trench structure within a semiconductor material. A gate electrode is isolated from the semiconductor material using gate insulating layers. Before the shield electrode is formed, spacer layers can be used form shield insulating layers along portions of the trench structure. The shield insulating layers are thicker than the gate insulating layers. In another embodiment, the shield insulating layers have variable thickness.

摘要翻译： 在一个实施例中，垂直绝缘栅场效应晶体管包括形成在半导体材料内的沟槽结构中的屏蔽电极。 栅电极使用栅极绝缘层与半导体材料隔离。 在形成屏蔽电极之前，间隔层可以沿沟槽结构的部分形成屏蔽绝缘层。 屏蔽绝缘层比栅极绝缘层厚。 在另一个实施例中，屏蔽绝缘层具有可变的厚度。

公开(公告)号：US08648412B1

公开(公告)日：2014-02-11

申请号：US13487479

申请日：2012-06-04

申请人： Peter A. Burke ,  Agajan Suwhanov ,  Prasad Venkatraman

发明人： Peter A. Burke ,  Agajan Suwhanov ,  Prasad Venkatraman

IPC分类号： H01L29/76 ,  H01L29/94

CPC分类号： H01L29/7813 ,  H01L21/26506 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/4933 ,  H01L29/66727 ,  H01L29/66734

摘要： In one embodiment, a structure for a trench power field effect transistor device with controlled, shallow, abrupt, body contact regions.

摘要翻译： 在一个实施例中，具有受控的，浅的，突然的身体接触区域的沟槽功率场效应晶体管器件的结构。

公开(公告)号：US08642425B2

公开(公告)日：2014-02-04

申请号：US13482920

申请日：2012-05-29

申请人： Peter A. Burke ,  Eric J. Ameele

发明人： Peter A. Burke ,  Eric J. Ameele

IPC分类号： H01L21/336

CPC分类号： H01L29/7813 ,  H01L21/02164 ,  H01L21/02211 ,  H01L21/02271 ,  H01L29/401 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/4933 ,  H01L29/66348 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7397

摘要： In one embodiment, a trench shield electrode layer is separated from a trench gate electrode by an inter-electrode dielectric layer. A conformal deposited dielectric layer is formed as part of a gate dielectric structure and further isolates the trench shield electrode from the trench gate electrode. The conformal deposited dielectric layer is formed using an improved high temperature oxide (HTO) low pressure chemical vapor deposition (LPCVD) process.

摘要翻译： 在一个实施例中，沟槽屏蔽电极层通过电极间介电层与沟槽栅电极分离。 形成共形沉积介电层作为栅极电介质结构的一部分，并进一步将沟槽屏蔽电极与沟槽栅电极隔离。 使用改进的高温氧化物（HTO）低压化学气相沉积（LPCVD）工艺形成共形沉积介电层。

公开(公告)号：US08043968B2

公开(公告)日：2011-10-25

申请号：US12764004

申请日：2010-04-20

申请人： Hao Cui ,  Peter A. Burke ,  Wilbur G. Catabay

发明人： Hao Cui ,  Peter A. Burke ,  Wilbur G. Catabay

IPC分类号： H01L21/00

CPC分类号： H01L21/76832 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76834 ,  H01L21/76883

摘要： Embodiments of the invention include a copper interconnect structure having increased electromigration lifetime. Such structures can include a semiconductor substrate having a copper layer formed thereon. A dielectric barrier stack is formed on the copper layer. The dielectric barrier stack includes a first portion formed adjacent to the copper layer and a second portion formed on the first portion, the first portion having improved adhesion to copper relative to the second portion and both portions are formed having resistance to copper diffusion. The invention also includes several embodiments for constructing such structures. Adhesion of the dielectric barrier stack to copper can be increased by plasma treating or ion implanting selected portions of the dielectric barrier stack with adhesion enhancing materials to increase the concentration of such materials in the stack.

摘要翻译： 本发明的实施例包括具有增加的电迁移寿命的铜互连结构。 这种结构可以包括其上形成有铜层的半导体衬底。 在铜层上形成介电阻挡层叠体。 电介质势垒叠层包括邻近铜层形成的第一部分和形成在第一部分上的第二部分，第一部分具有相对于第二部分提高的对铜的粘附性，并且两个部分形成为具有耐铜扩散性。 本发明还包括用于构造这种结构的几个实施例。 可以通过等离子体处理或离子注入电介质阻挡层的选定部分与粘合增强材料来增加电介质阻挡层与铜的附着，以增加堆叠中这种材料的浓度。

公开(公告)号：US20110127603A1

公开(公告)日：2011-06-02

申请号：US13022628

申请日：2011-02-07

申请人： Peter A. Burke ,  Duane B. Barber ,  Brian Pratt

发明人： Peter A. Burke ,  Duane B. Barber ,  Brian Pratt

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66727 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42376 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66734 ,  H01L29/7809 ,  H01L29/7811 ,  H01L29/7813

摘要： A semiconductor component that includes gate electrodes and shield electrodes and a method of manufacturing the semiconductor component. A semiconductor material has a device region, a gate contact region, a termination region, and a drain contact region. One or more device trenches is formed in the device region and one or more termination trenches is formed in the edge termination region. Shielding electrodes are formed in portions of the device trenches that are adjacent their floors. A gate dielectric material is formed on the sidewalls of the trenches in the device region and gate electrodes are formed over and electrically isolated from the shielding electrodes. The gate electrodes in the trenches in the device region are connected to the gate electrodes in the trenches in the gate contact region. The shielding electrodes in the trenches in the device region are connected to the shielding electrodes in the termination region.

摘要翻译： 包括栅电极和屏蔽电极的半导体部件和制造半导体部件的方法。 半导体材料具有器件区域，栅极接触区域，端接区域和漏极接触区域。 在器件区域中形成一个或多个器件沟槽，并且在边缘端接区域中形成一个或多个端接沟槽。 屏蔽电极形成在与它们的地板相邻的器件沟槽的部分中。 在器件区域中的沟槽的侧壁上形成栅极电介质材料，并且在屏蔽电极之间形成栅电极并与屏蔽电极电绝缘。 器件区域中的沟槽中的栅电极连接到栅极接触区域中的沟槽中的栅电极。 器件区域的沟槽中的屏蔽电极与端接区域中的屏蔽电极相连。

公开(公告)号：US20110079876A1

公开(公告)日：2011-04-07

申请号：US12962579

申请日：2010-12-07

申请人： Sallie Hose ,  Peter A. Burke ,  Li Jiang ,  Sudhama C. Shastri

发明人： Sallie Hose ,  Peter A. Burke ,  Li Jiang ,  Sudhama C. Shastri

IPC分类号： H01L29/92 ,  H01L21/02

CPC分类号： H01L23/5227 ,  H01L23/5223 ,  H01L23/5228 ,  H01L23/53238 ,  H01L24/05 ,  H01L27/0629 ,  H01L28/10 ,  H01L28/24 ,  H01L28/40 ,  H01L2224/05624 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/12035 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/19041 ,  H01L2924/00014 ,  H01L2924/00

摘要： A semiconductor component and methods for manufacturing the semiconductor component that includes a monolithically integrated passive device. In accordance with embodiments, the monolithically integrated passive device includes an inductor formed from damascene structures.

摘要翻译： 一种半导体元件及其制造方法，该半导体元件包括单片集成无源器件。 根据实施例，单片集成无源器件包括由镶嵌结构形成的电感器。

公开(公告)号：US20110044851A1

公开(公告)日：2011-02-24

申请号：US12939239

申请日：2010-11-04

申请人： Michael A. Centanni ,  Peter A. Burke

发明人： Michael A. Centanni ,  Peter A. Burke

IPC分类号： A61L9/015

CPC分类号： A61L2/208 ,  A61L2/202 ,  A61L2/206 ,  A61L9/015 ,  A61L2202/13

摘要： A method and apparatus for aerating a region exposed to a gaseous/vaporous sterilant. A catalytic destroyer and a reactive chemical unit are used to reduce the concentration of the gaseous/vaporous sterilant within the region. The reactive chemical unit includes a chemistry that is chemically reactive with the gaseous/vaporous sterilant. In one embodiment, the gaseous/vaporous sterilant is vaporized hydrogen peroxide and the chemistry of the reactive chemical unit includes thiosulfate and iodide.

摘要翻译： 用于对暴露于气体/蒸气灭菌剂的区域进行曝气的方法和装置。 催化破坏剂和反应性化学单元用于降低该区域内气态/蒸气灭菌剂的浓度。 反应性化学单元包括与气态/蒸气灭菌剂化学反应的化学物质。 在一个实施方案中，气态/蒸气灭菌剂是蒸发的过氧化氢，并且反应性化学单元的化学性质包括硫代硫酸盐和碘化物。

公开(公告)号：US07884430B2

公开(公告)日：2011-02-08

申请号：US12710477

申请日：2010-02-23

申请人： Richard J. Carter ,  Peter A. Burke ,  Verne C. Hornback ,  Thomas Rueckes ,  Claude L. Bertin

发明人： Richard J. Carter ,  Peter A. Burke ,  Verne C. Hornback ,  Thomas Rueckes ,  Claude L. Bertin

IPC分类号： H01L29/84

CPC分类号： H01H1/0094 ,  Y10S977/724 ,  Y10S977/732 ,  Y10S977/943

摘要： The present invention is directed to structures and methods of fabricating electromechanical memory cells having nanotube crossbar elements. Such memory cells include a substrate having transistor with a contact that electrically contacts with the transistor. A first support layer is formed over the substrate with an opening that defines a lower chamber above the electrical contact. A nanotube crossbar element is arranged to span the lower chamber. A second support layer is formed with an opening that defines a top chamber above the lower chamber, the top chamber including an extension region that extends beyond an edge of the lower chamber to expose a portion of the top surface of the first support layer. A roof layer covers the top of the top chamber and includes an aperture that exposes a portion of the extension region of the top chamber and includes a plug that extends into the aperture in the roof layer to seal the top and bottom chambers. The memory cell further includes an electrode that overlies the crossbar element such that electrical signals can activate the electrode to attract or repel the crossbar element to set a memory state for the transistor.

摘要翻译： 本发明涉及制造具有纳米管横杆元件的机电存储器单元的结构和方法。 这种存储单元包括具有与晶体管电接触的接触的晶体管的衬底。 第一支撑层形成在衬底上，其开口限定了电触点上方的下腔室。 纳米管横杆元件布置成跨越下室。 第二支撑层形成有开口，所述开口限定在所述下腔室上方的顶部腔室，所述顶部腔室包括延伸超出所述下部腔室的边缘以暴露所述第一支撑层的顶部表面的一部分的延伸区域。 屋顶层覆盖顶部室的顶部，并且包括露出顶部室的延伸区域的一部分并且包括延伸到顶部层中的孔中以密封顶部和底部室的插塞的孔。 存储单元还包括覆盖在横杆元件上的电极，使得电信号可以激活电极以吸引或排斥交叉开关元件以设置晶体管的存储状态。

公开(公告)号：US20090267187A1

公开(公告)日：2009-10-29

申请号：US12108361

申请日：2008-04-23

申请人： Sallie Hose ,  Derryl Allman ,  Peter A. Burke ,  Ponce Saopraseuth

发明人： Sallie Hose ,  Derryl Allman ,  Peter A. Burke ,  Ponce Saopraseuth

IPC分类号： H01L29/92 ,  H01L21/02

CPC分类号： H01L28/75

摘要： An energy storage device such as a metal-insulator-metal capacitor and a method for manufacturing the energy storage device. The metal-insulator-metal capacitor includes an insulating material positioned between a bottom electrode or bottom plate and a top electrode or top plate. The surface area of the bottom electrode is greater than the surface area of the insulating material and the surface area of the insulating material is greater than the surface area of the top electrode. The top electrode and the insulating layer have edges that are laterally within and spaced apart from edges of the bottom electrode. A protective layer covers the top electrode, the edges of the top electrode, and the portions of the insulating layer that are uncovered by the top electrode. The protective layer serves as an etch mask during the formation of the bottom electrode.

摘要翻译： 诸如金属 - 绝缘体 - 金属电容器的能量存储装置和用于制造储能装置的方法。 金属 - 绝缘体 - 金属电容器包括位于底部电极或底板与顶部电极或顶板之间的绝缘材料。 底部电极的表面积大于绝缘材料的表面积，并且绝缘材料的表面积大于顶部电极的表面积。 顶部电极和绝缘层具有横向在底部电极的边缘内并与其间隔开的边缘。 保护层覆盖顶部电极，顶部电极的边缘和绝缘层的未被顶部电极覆盖的部分。 在形成底部电极期间，保护层用作蚀刻掩模。