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146 条记录 (耗时 0.023 秒)

    Memory cells having a plurality of resistance variable materials
    84.
    发明授权
    Memory cells having a plurality of resistance variable materials 有权
    存储单元具有多个电阻变化材料

    公开(公告)号：US08964448B2

    公开(公告)日：2015-02-24

    申请号：US13570772

    申请日：2012-08-09

    申请人： Ugo Russo ,  Andrea Redaelli ,  Fabio Pellizzer

    发明人： Ugo Russo ,  Andrea Redaelli ,  Fabio Pellizzer

    IPC分类号： G11C11/00

    CPC分类号： G11C13/0004 ,  G11C11/5678 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/008 ,  H01L45/06 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/14 ,  H01L45/145 ,  H01L45/16

    摘要： Resistance variable memory cells having a plurality of resistance variable materials and methods of operating and forming the same are described herein. As an example, a resistance variable memory cell can include a plurality of resistance variable materials located between a plug material and an electrode material. The resistance variable memory cell also includes a first conductive material that contacts the plug material and each of the plurality of resistance variable materials and a second conductive material that contacts the electrode material and each of the plurality of resistance variable materials.

    摘要翻译： 具有多个电阻变化材料的电阻变量存储单元及其操作和形成方法在此描述。 作为示例，电阻可变存储单元可以包括位于插塞材料和电极材料之间的多个电阻变化材料。 电阻可变存储单元还包括接触插塞材料和多个电阻可变材料中的每一个的第一导电材料和接触电极材料和多个电阻可变材料中的每一个的第二导电材料。

    Etch bias homogenization
    85.
    发明授权
    Etch bias homogenization 有权
    蚀刻偏差匀浆

    公开(公告)号：US08785314B2

    公开(公告)日：2014-07-22

    申请号：US13463245

    申请日：2012-05-03

    申请人： Fabio Pellizzer ,  Hernan A. Castro ,  Eddie T. Flores

    发明人： Fabio Pellizzer ,  Hernan A. Castro ,  Eddie T. Flores

    IPC分类号： H01L21/44 ,  H01L21/3213 ,  H01L21/768

    CPC分类号： H01L45/1273 ,  H01L21/32134 ,  H01L21/76838 ,  H01L27/101 ,  H01L27/2427 ,  H01L27/2436 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1675

    摘要： Methods and memory devices formed using etch bias homogenization are provided. One example method of forming a memory device using etch bias homogenization includes forming conductive material at respective levels over a substrate. Each respective level of conductive material is electrically coupled to corresponding circuitry on the substrate during patterning of the respective level of conductive material so that each respective level of conductive material has a homogenized etch bias during patterning thereof. Each respective level of conductive material electrically coupled to corresponding circuitry on the substrate is patterned.

    摘要翻译： 提供了使用蚀刻偏压均化形成的方法和存储器件。 使用蚀刻偏压均化形成存储器件的一个示例性方法包括在衬底上形成相应电平的导电材料。 在对相应级别的导电材料进行图案化期间，每个相应级别的导电材料电耦合到衬底上的对应电路，使得每个相应级别的导电材料在其图案化期间具有均质化的蚀刻偏压。 电耦合到衬底上的对应电路的每个相应级别的导电材料被图案化。

    Vertical mosfet transistor, in particular operating as a selector in nonvolatile memory devices
    86.
    发明授权
    Vertical mosfet transistor, in particular operating as a selector in nonvolatile memory devices 有权
    垂直mosfet晶体管，特别是在非易失性存储器件中用作选择器

    公开(公告)号：US08766344B2

    公开(公告)日：2014-07-01

    申请号：US12862624

    申请日：2010-08-24

    申请人： Fabio Pellizzer ,  Agostino Pirovano

    发明人： Fabio Pellizzer ,  Agostino Pirovano

    IPC分类号： H01L45/00 ,  G11C13/00

    CPC分类号： H01L29/7827 ,  G11C13/0004 ,  H01L27/2454 ,  H01L29/42392 ,  H01L29/665 ,  H01L29/66666 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144

    摘要： A vertical MOSFET transistor is formed in a body of semiconductor material having a surface. The transistor includes a buried conductive region of a first conductivity type; a channel region of a second conductivity type, arranged on top of the buried conductive region; a surface conductive region of the first conductivity type, arranged on top of the channel region and the buried conductive region; a gate insulation region, extending at the sides of and contiguous to the channel region; and a gate region extending at the sides of and contiguous to the gate insulation region.

    摘要翻译： 在具有表面的半导体材料的主体中形成垂直MOSFET晶体管。 晶体管包括第一导电类型的掩埋导电区域; 布置在所述掩埋导电区域的顶部上的第二导电类型的沟道区域; 第一导电类型的表面导电区域布置在沟道区域和掩埋导电区域的顶部上; 栅极绝缘区域，在沟道区域的两侧延伸; 以及在栅极绝缘区域的侧面延伸并且与栅极绝缘区域邻接的栅极区域。

    Semiconductor constructions and memory arrays
    87.
    发明授权
    Semiconductor constructions and memory arrays 有权
    半导体结构和存储器阵列

    公开(公告)号：US08686394B2

    公开(公告)日：2014-04-01

    申请号：US13551873

    申请日：2012-07-18

    申请人： Fabio Pellizzer ,  Cinzia Perrone

    发明人： Fabio Pellizzer ,  Cinzia Perrone

    IPC分类号： H01L29/06

    CPC分类号： H01L21/31111 ,  H01L21/02115 ,  H01L27/2409 ,  H01L45/06 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1608 ,  H01L45/1675

    摘要： Some embodiments include methods of forming semiconductor constructions. Carbon-containing material is formed over oxygen-sensitive material. The carbon-containing material and oxygen-sensitive material together form a structure having a sidewall that extends along both the carbon-containing material and the oxygen-sensitive material. First protective material is formed along the sidewall. The first protective material extends across an interface of the carbon-containing material and the oxygen-sensitive material, and does not extend to a top region of the carbon-containing material. Second protective material is formed across the top of the carbon-containing material, with the second protective material having a common composition to the first protective material. The second protective material is etched to expose an upper surface of the carbon-containing material. Some embodiments include semiconductor constructions, memory arrays and methods of forming memory arrays.

    摘要翻译： 一些实施例包括形成半导体结构的方法。 含氧材料在氧敏感材料上形成。 含碳材料和氧敏感材料一起形成具有沿着含碳材料和氧敏感材料两者延伸的侧壁的结构。 第一保护材料沿侧壁形成。 第一保护材料延伸穿过含碳材料和氧敏感材料的界面，并且不延伸到含碳材料的顶部区域。 第二保护材料横跨含碳材料的顶部形成，第二保护材料与第一保护材料具有共同的组成。 蚀刻第二保护材料以暴露含碳材料的上表面。 一些实施例包括半导体构造，存储器阵列和形成存储器阵列的方法。