公开(公告)号：US06429080B2

公开(公告)日：2002-08-06

申请号：US09793517

申请日：2001-02-27

申请人： Toshiharu Furukawa ,  David V. Horak ,  Howard L. Kalter

发明人： Toshiharu Furukawa ,  David V. Horak ,  Howard L. Kalter

IPC分类号： H01L21336

CPC分类号： G11C11/565 ,  G11C11/404 ,  H01L27/108 ,  H01L27/10864 ,  H01L27/1087 ,  H01L27/10882

摘要： A multi-level memory cell capable of storing two or three bits of digital data occupies only four lithographic squares and requires only one or two logic level voltage sources, respectively. High noise immunity derives from integration of the multi-level signal in the memory cell directly from logic level digital signals applied to two capacitors (as well as the bit line for the eight level mode of operation) by using capacitors having different values in order to avoid digital-to-analog conversion during writing. The capacitors can be simultaneously written and read to reduce memory cycle time. Transistor channels and capacitor connections are formed on adjacent semiconductor pillars using plugs of semiconductor material between pillars as common gate structures and connections. Opposite surfaces of the pillars also serve as storage nodes with common capacitor plates formed by conformal deposition between rows of plugs and pillars.

摘要翻译： 能够存储两位或三位数字数据的多级存储器单元仅占用四个光刻平面，并且仅分别仅需要一个或两个逻辑电平电压源。 通过使用具有不同值的电容器，可以直接从施加到两个电容器的逻辑电平数字信号（以及八电平工作模式的位线）将存储单元中的多电平信号集成到高抗噪声性能 避免在写入过程中进行数模转换。 电容器可以同时写入和读取，以减少存储周期时间。 晶体管通道和电容器连接使用在柱之间的半导体材料的塞子作为公共栅极结构和连接形成在相邻的半导体柱上。 支柱的相对表面还用作具有通过塞子和柱之间的共形沉积形成的公共电容器板的存储节点。

公开(公告)号：US06380027B2

公开(公告)日：2002-04-30

申请号：US09225127

申请日：1999-01-04

申请人： Toshiharu Furukawa ,  Jeffrey P. Gambino ,  Edward W. Kiewra ,  Jack A. Mandelman ,  Carl J. Radens ,  William R. Tonti ,  Mary E. Weybright

发明人： Toshiharu Furukawa ,  Jeffrey P. Gambino ,  Edward W. Kiewra ,  Jack A. Mandelman ,  Carl J. Radens ,  William R. Tonti ,  Mary E. Weybright

IPC分类号： H01L21242

CPC分类号： H01L27/10876 ,  H01L27/10823 ,  H01L27/10829 ,  H01L27/10894

摘要： A structure and method for simultaneously forming array structures and support structures on a substrate comprises forming the array structures to have a V-groove, forming the support structures to have a planar surface, and simultaneously forming a first oxide in the V-groove and a second oxide in the planar surface, wherein the first oxide is thicker than the second oxide.

摘要翻译： 用于在衬底上同时形成阵列结构和支撑结构的结构和方法包括：形成阵列结构以具有V形槽，形成支撑结构以具有平坦表面，同时在V形槽中形成第一氧化物，以及 其中所述第一氧化物比所述第二氧化物厚。

公开(公告)号：US06358813B1

公开(公告)日：2002-03-19

申请号：US09713766

申请日：2000-11-15

申请人： Steven J. Holmes ,  Charles Black ,  David J. Frank ,  Toshiharu Furukawa ,  Mark C. Hakey ,  David V. Horak ,  William Hsioh-Lien Ma ,  Keith R. Milkove ,  Kathryn W. Guarini

发明人： Steven J. Holmes ,  Charles Black ,  David J. Frank ,  Toshiharu Furukawa ,  Mark C. Hakey ,  David V. Horak ,  William Hsioh-Lien Ma ,  Keith R. Milkove ,  Kathryn W. Guarini

IPC分类号： H01L2120

CPC分类号： H01L28/92

摘要： Described is a method of increasing the capacitance of semiconductor capacitors by providing a first solid-state electrode pattern on a semiconductor medium, etching topographic features on said first electrode pattern in a manner effective in increasing the surface area of said first electrode pattern, depositing a dielectric layer upon said electrode pattern that substantially conforms to said topographic features, and depositing a second solid-state electrode pattern upon said dielectric layer and sufficiently insulated from said first solid-state electrode pattern so as to create a capacitance with said first solid-state electrode pattern.

摘要翻译： 描述了通过在半导体介质上提供第一固态电极图案来增加半导体电容器的电容的方法，以有效增加所述第一电极图案的表面积的方式蚀刻所述第一电极图案上的地形特征， 所述电极图案上的电介质层基本上符合所述形貌特征，并且在所述电介质层上沉积第二固态电极图案，并且与所述第一固态电极图案充分绝缘，从而产生具有所述第一固态的电容 电极图案。

公开(公告)号：US06282115B1

公开(公告)日：2001-08-28

申请号：US09469275

申请日：1999-12-22

申请人： Toshiharu Furukawa ,  David V. Horak ,  Howard L. Kalter

发明人： Toshiharu Furukawa ,  David V. Horak ,  Howard L. Kalter

IPC分类号： G11C1124

CPC分类号： G11C11/565 ,  G11C11/404 ,  H01L27/108 ,  H01L27/10864 ,  H01L27/1087 ,  H01L27/10882

摘要： A multi-level memory cell capable of storing two or three bits of digital data occupies only four lithographic squares and requires only one or two logic level voltage sources, respectively. High noise immunity derives from integration of the multi-level signal in the memory cell directly from logic level digital signals applied to two capacitors (as well as the bit line for the eight level mode of operation) by using capacitors having different values in order to avoid digital-to-analog conversion during writing. The capacitors can be simultaneously written and read to reduce memory cycle time. Transistor channels and capacitor connections are formed on adjacent semiconductor pillars using plugs of semiconductor material between pillars as common gate structures and connections. Opposite surfaces of the pillars also serve as storage nodes with common capacitor plates formed by conformal deposition between rows of plugs and pillars.

摘要翻译： 能够存储两位或三位数字数据的多级存储器单元仅占用四个光刻平面，并且仅分别仅需要一个或两个逻辑电平电压源。 通过使用具有不同值的电容器，可以直接从施加到两个电容器的逻辑电平数字信号（以及八电平工作模式的位线）将存储单元中的多电平信号集成到高抗噪声性能 避免在写入过程中进行数模转换。 电容器可以同时写入和读取，以减少存储周期时间。 晶体管通道和电容器连接使用在柱之间的半导体材料的塞子作为公共栅极结构和连接形成在相邻的半导体柱上。 支柱的相对表面还用作具有通过塞子和柱之间的共形沉积形成的公共电容器板的存储节点。

公开(公告)号：US06277543B1

公开(公告)日：2001-08-21

申请号：US09369412

申请日：1999-08-05

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Paul A. Rabidoux

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Paul A. Rabidoux

IPC分类号： G03C500

CPC分类号： G03F7/70466 ,  G03F7/038 ,  G03F7/2022 ,  H01L21/0274

摘要： The preferred embodiment of the present invention overcomes the limitations of the prior art by providing a method to form unlinked features using hybrid resist. The method uses a trim process in order to trim the linking features from the “loops” formed by the hybrid resist. This allows the method to form a plurality of unlinked features rather than the loops. In order to trim the ends, a relatively larger trim area is formed adjacent the narrow feature line, either by a second exposure step or by utilizing a grey scale reticle. The broader or wider open area allows features to be formed in the narrow feature lines and being trimmed from the relatively large areas, thereby resulting in district features rather than loops.

摘要翻译： 本发明的优选实施例通过提供使用混合抗蚀剂形成不连接特征的方法来克服现有技术的局限性。 该方法使用修剪工艺来修剪由混合抗蚀剂形成的“环”的连接特征。 这允许该方法形成多个未链接的特征而不是循环。 为了修剪端部，通过第二曝光步骤或通过利用灰度光罩，形成与窄特征线相邻的相对较大的修整区域。 更宽或更宽的开放区域允许在窄特征线中形成特征并且从相对较大的区域修剪特征，从而导致区域特征而不是环。

公开(公告)号：US06251755B1

公开(公告)日：2001-06-26

申请号：US09296368

申请日：1999-04-22

申请人： Toshiharu Furukawa ,  John Joseph Ellis-Monaghan ,  James Albert Slinkman

发明人： Toshiharu Furukawa ,  John Joseph Ellis-Monaghan ,  James Albert Slinkman

IPC分类号： H01L2104

CPC分类号： H01L21/18 ,  G01Q80/00 ,  H01L21/225 ,  H01L21/2255 ,  H01L21/2258 ,  H01L21/67092 ,  H01L29/1029 ,  H01L29/1045 ,  H01L29/802 ,  Y10S977/855

摘要： The present invention employs a scanned atomic force probe to physical incorporate impurity atoms (dopant or bandgap) into a semiconductor substrate so that the impurity atoms have high resolution and improved placement. Specifically, the method of the present invention comprising a step of physically contacting a semiconductor surface having a layer of a dopant/bandgap source material thereon such that upon said physical contact impurity atoms from the dopant/bandgap source material are driven into the semiconductor substrate.

摘要翻译： 本发明采用扫描的原子力探针将杂质原子（掺杂剂或带隙）物理并入到半导体衬底中，使得杂质原子具有高分辨率和改进的放置。 具体地说，本发明的方法包括使其上具有掺杂剂/带隙源材料层的半导体表面物理接触的步骤，使得在所述物理接触时，杂质来自掺杂剂/带隙源材料的杂质被驱动到半导体衬底中。

公开(公告)号：US06207493B1

公开(公告)日：2001-03-27

申请号：US09136586

申请日：1998-08-19

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Thomas S. Kanarsky

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Thomas S. Kanarsky

IPC分类号： H01L218242

CPC分类号： H01L27/10885 ,  H01L21/2254 ,  H01L21/2257 ,  H01L21/268 ,  H01L21/743 ,  H01L27/10876

摘要： The present invention provides methods of forming an out-diffused bitline in a semiconductor substrate by utilizing a laser annealing step wherein the dopant material in the trench region is out-diffused into the semiconductor substrate. The out-diffused bitline can also be formed utilizing an ion implantation step.

公开(公告)号：US6114725A

公开(公告)日：2000-09-05

申请号：US93928

申请日：1998-06-09

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Howard L. Kalter ,  Jack A. Mandelman ,  Paul A. Rabidoux ,  Jeffrey J. Welser

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Howard L. Kalter ,  Jack A. Mandelman ,  Paul A. Rabidoux ,  Jeffrey J. Welser

IPC分类号： H01L21/8242 ,  H01L21/8247 ,  H01L27/108 ,  H01L27/115 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H01L29/76 ,  H01L29/94 ,  H01L31/113 ,  H01L31/119 ,  H01L31/62

CPC分类号： H01L27/11556 ,  H01L27/10808 ,  H01L27/10823 ,  H01L27/10841 ,  H01L27/10897 ,  H01L27/115

摘要： A densely packed array of vertical semiconductor devices having pillars and methods of making thereof are disclosed. The array has rows of wordlines and columns of bitlines. The array has vertical pillars, each having two wordlines, one active and the other passing for each cell. Two wordlines are formed per pillar on opposite pillar sidewalls which are along the row direction. The threshold voltage of the pillar device is raised on the side of the pillar touching the passing wordline, thereby permanently shutting off the pillar device during the cell operation and isolating the pillar from the voltage variations on the passing wordline. The isolated wordlines allow individual cells to be addressed and written via direct tunneling, in both volatile and non-volatile memory cell configurations. For Gbit DRAM application, stack or trench capacitors may be formed on the pillars, or in trenches surrounding the pillars, respectively.

摘要翻译： 公开了一种具有支柱的紧密堆叠的垂直半导体器件阵列及其制造方法。 该阵列具有字线和位线列。 阵列具有垂直柱，每个具有两个字线，一个有效，另一个通过每个单元格。 在沿着行方向的相对的支柱侧壁上的每个柱形成两个字线。 支柱装置的阈值电压在柱体侧面升高，接触通过字线，从而在电池工作期间永久地关闭支柱装置，并将支柱与通过字线上的电压变化隔离。 孤立的字线允许在易失性和非易失性存储单元配置中通过直接隧道寻址和写入各个单元。 对于Gbit DRAM应用，可以在支柱上或在柱子周围的沟槽中分别形成堆叠或沟槽电容器。

公开(公告)号：US6100172A

公开(公告)日：2000-08-08

申请号：US182173

申请日：1998-10-29

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Paul A. Rabidoux

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Paul A. Rabidoux

IPC分类号： H01L21/033 ,  H01L21/308 ,  H01L21/336 ,  H01L21/768 ,  H01L21/822 ,  H01L29/78 ,  H01L21/22 ,  H01L21/425 ,  H01L21/8234

CPC分类号： H01L29/66613 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/76895 ,  H01L21/822 ,  H01L29/7835

摘要： The present invention provides a method for forming self-aligned spacers on the horizontal surfaces while removing spacer material from the vertical surfaces. The preferred method uses a resist that can be made insoluble to developer by the use of an implant. By conformally depositing the resist over a substrate having both vertical and horizontal surfaces, implanting the resist, and developing the resist, the resist is removed from the vertical surfaces while remaining on the horizontal surfaces. Thus, a self-aligned spacer is formed on the horizontal surfaces while the spacer material is removed from the vertical surfaces. This horizontal-surface spacer can then be used in further fabrication. The preferred method can be used in many different processes where there is exists a need to differentially process the vertical and horizontal surfaces of a substrate.

摘要翻译： 本发明提供一种用于在水平表面上形成自对准间隔物的方法，同时从垂直表面移除间隔物材料。 优选的方法使用可以通过使用植入物使其不溶于显影剂的抗蚀剂。 通过在具有垂直和水平表面的基底上保形地沉积抗蚀剂，植入抗蚀剂并显影抗蚀剂，在保持在水平表面上的同时将抗蚀剂从垂直表面上除去。 因此，当从垂直表面移除间隔物材料时，在水平表面上形成自对准间隔物。 然后可以将该水平表面间隔件用于进一步制造。 优选的方法可以用于许多不同的工艺，其中存在需要对衬底的垂直和水平表面进行差异化处理。

公开(公告)号：US5831301A

公开(公告)日：1998-11-03

申请号：US14523

申请日：1998-01-28

申请人： David Vaclav Horak ,  Toshiharu Furukawa ,  Steven John Holmes ,  Mark Charles Hakey ,  William Hsioh-Lien Ma ,  Jack Allan Mandelman

发明人： David Vaclav Horak ,  Toshiharu Furukawa ,  Steven John Holmes ,  Mark Charles Hakey ,  William Hsioh-Lien Ma ,  Jack Allan Mandelman

IPC分类号： H01L21/76 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/76

CPC分类号： H01L27/10864 ,  H01L27/10841

摘要： A memory cell including a substrate, at least one deep trench capacitor in the substrate, at least one FET in the substrate disposed over at least a portion of the at least one deep trench capacitor, and at least one isolation region in the substrate surrounding the at least one FET and having a greater depth than the at least one FET. The at least one FET includes a gate disposed over at least a portion of the at least one deep trench capacitor and doped regions arranged on adjacent sides of the gate and separated from the gate by an insulating layer.

摘要翻译： 存储单元，包括衬底，衬底中的至少一个深沟槽电容器，设置在所述至少一个深沟槽电容器的至少一部分上的所述衬底中的至少一个FET以及所述衬底中的至少一个隔离区域， 至少一个FET并且具有比所述至少一个FET更大的深度。 所述至少一个FET包括设置在所述至少一个深沟槽电容器的至少一部分上的栅极和布置在栅极的相邻侧上的掺杂区域，并且通过绝缘层与栅极分离。