公开(公告)号：US10008500B2

公开(公告)日：2018-06-26

申请号：US15174273

申请日：2016-06-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Carl J. Radens

IPC: H01L27/11 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/78

CPC classification number: H01L27/0922 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/823871 ,  H01L21/823878 ,  H01L27/0207 ,  H01L27/1104 ,  H01L27/1211 ,  H01L29/7842 ,  H01L29/7848

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to segmented or cut finFET structures and methods of manufacture. The structure includes at least one logic finFET device having a fin of a first length, and at least one memory finFET device having a fin of a second length. The second length is shorter than the first length.

公开(公告)号：US10002965B2

公开(公告)日：2018-06-19

申请号：US15298648

申请日：2016-10-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Ruilong Xie ,  Tenko Yamashita

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/165 ,  H01L27/092 ,  H01L21/8238

CPC classification number: H01L29/66795 ,  H01L21/225 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/66803 ,  H01L29/7848 ,  H01L29/785

Abstract: A method of forming semiconductor devices that includes forming an oxide that is doped with a punch through dopant on a surface of a first semiconductor material having a first lattice dimension, and diffusing punch through dopant from the oxide into the semiconductor material to provide a punch through stop region. The oxide may then be removed. A second semiconductor material may be formed having a second lattice dimension on the first semiconductor material having the first lattice dimension. A difference between the first lattice dimension and the second lattice dimension forms a strain in the second semiconductor material. A gate structure and source and drain regions are formed on the second semiconductor material.

公开(公告)号：US20180122913A1

公开(公告)日：2018-05-03

申请号：US15338925

申请日：2016-10-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Kangguo Cheng ,  Tenko Yamashita ,  Chun-chen Yeh

IPC: H01L29/417 ,  H01L23/525 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/762 ,  H01L21/768

CPC classification number: H01L29/41791 ,  H01L21/76224 ,  H01L23/5256 ,  H01L29/0649 ,  H01L29/0676 ,  H01L29/66795 ,  H01L29/785

Abstract: Structures for a vertical-transport field-effect transistor and an electrical fuse integrated into an integrated circuit, and methods of fabricating a vertical-transport field-effect transistor and an electrical fuse integrated into an integrated circuit. A doped semiconductor layer that includes a first region with a first electrode of the vertical electrical fuse and a second region with a first source/drain region of the vertical-transport field effect transistor. A semiconductor fin is formed on the first region of the doped semiconductor layer, and a fuse link is formed on the second region of the doped semiconductor layer. A second source/drain region is formed that is coupled with the fin. A gate structure is arranged vertically between the first source/drain region and the second source/drain region. A second electrode of the vertical fuse is formed such that the fuse link is arranged vertically between the first electrode and the second electrode.

公开(公告)号：US09960271B1

公开(公告)日：2018-05-01

申请号：US15490255

申请日：2017-04-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Chun-chen Yeh ,  Tenko Yamashita ,  Kangguo Cheng

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/311 ,  H01L27/088

CPC classification number: H01L29/7827 ,  H01L21/31111 ,  H01L21/823418 ,  H01L21/823468 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/6656 ,  H01L29/66666

Abstract: An integrated circuit and method are disclosed. In the method, a stack of sacrificial layers is formed on a semiconductor layer such that a first portion of the stack has an extra sacrificial layer as compared to a second portion. First and second multi-layer fins are etched through the first and second portions and into the semiconductor layer. First and second vertical field effect transistors (VFETs) are formed using the fins. During VFET formation, multiple etch processes are performed to remove the sacrificial layers. The last of these etch processes is a selective isotropic etch process that removes the extra sacrificial layer and etches back first and second upper dielectric spacers on the first and second multi-layer fins. Due to the extra sacrificial layer, the first upper dielectric spacer will be taller than the second and the first VFET will have a higher threshold voltage than the second.

公开(公告)号：US09960168B2

公开(公告)日：2018-05-01

申请号：US14582655

申请日：2014-12-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Veeraraghavan S. Basker ,  Kangguo Cheng ,  Benjamin Ryan Cipriany ,  Ramachandra Divakaruni ,  Brian J. Greene ,  Ali Khakifirooz ,  Byeong Yeol Kim ,  William Larsen Nicoll

IPC: H01L21/20 ,  H01L27/108 ,  H01L21/324 ,  H01L21/84 ,  H01L29/94 ,  H01L27/12 ,  H01L21/02 ,  H01L21/285 ,  H01L21/768

CPC classification number: H01L27/10829 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/28518 ,  H01L21/324 ,  H01L21/76895 ,  H01L21/845 ,  H01L27/10826 ,  H01L27/10867 ,  H01L27/10879 ,  H01L27/1211 ,  H01L29/945

Abstract: Structures and methods for deep trench capacitor connections are disclosed. The structure includes a reduced diameter top portion of the capacitor conductor. This increases the effective spacing between neighboring deep trench capacitors. Silicide or additional polysilicon are then deposited to complete the connection between the deep trench capacitor and a neighboring transistor.

公开(公告)号：US09947774B2

公开(公告)日：2018-04-17

申请号：US14925630

申请日：2015-10-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Ruilong Xie ,  Tenko Yamashita

IPC: H01L29/66 ,  H01L21/225 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/225 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/66803 ,  H01L29/7848 ,  H01L29/785

Abstract: A method of forming semiconductor devices that includes forming an oxide that is doped with a punch through dopant on a surface of a first semiconductor material having a first lattice dimension, and diffusing punch through dopant from the oxide into the semiconductor material to provide a punch through stop region. The oxide may then be removed. A second semiconductor material may be formed having a second lattice dimension on the first semiconductor material having the first lattice dimension. A difference between the first lattice dimension and the second lattice dimension forms a strain in the second semiconductor material. A gate structure and source and drain regions are formed on the second semiconductor material.

公开(公告)号：US09935018B1

公开(公告)日：2018-04-03

申请号：US15436281

申请日：2017-02-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Chun-Chen Yeh ,  Tenko Yamashita ,  Kangguo Cheng

IPC: H01L21/00 ,  H01L27/00 ,  H01L29/00 ,  H01L21/8238 ,  H01L21/324 ,  H01L21/306 ,  H01L21/308 ,  H01L29/66 ,  H01L27/092 ,  H01L29/78 ,  H01L29/423

CPC classification number: H01L21/823885 ,  H01L21/30604 ,  H01L21/3085 ,  H01L21/823418 ,  H01L21/823468 ,  H01L21/823487 ,  H01L21/823814 ,  H01L21/82385 ,  H01L21/823864 ,  H01L27/088 ,  H01L27/092 ,  H01L29/42376 ,  H01L29/6656 ,  H01L29/66666 ,  H01L29/7827

Abstract: One illustrative method disclosed herein includes, among other things, forming first and second vertically-oriented channel (VOC) semiconductor structures for, respectively, first and second vertical transistor devices, and forming first and second top spacers, respectively, around the first and second VOC structures, wherein the first spacer thickness is greater than the second spacer thickness. In this example, the method also includes performing at least one epitaxial deposition process to form a first top source/drain structure around the first VOC structure and above the first top spacer and a second top source/drain structure around the second VOC structure and above the second top spacer, and performing an anneal process so as to cause dopants in the first and second doped top source/drain structures to migrate into, respectively, the first and second VOC structures.

公开(公告)号：US09917081B2

公开(公告)日：2018-03-13

申请号：US15181676

申请日：2016-06-14

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Kangguo Cheng ,  Junli Wang ,  Ruilong Xie ,  Tenko Yamashita

IPC: H01L27/108 ,  H01L27/06 ,  H01L29/78 ,  H01L29/93 ,  H01L29/10

CPC classification number: H01L27/0629 ,  H01L21/3083 ,  H01L21/3086 ,  H01L21/823431 ,  H01L27/0733 ,  H01L29/1083 ,  H01L29/66174 ,  H01L29/66537 ,  H01L29/6656 ,  H01L29/785 ,  H01L29/93

Abstract: A semiconductor device includes a semiconductor substrate having a fin-type field effect transistor (finFET) on a first region and a fin varactor on a second region. The finFET includes a first semiconductor fin that extends from an upper finFET surface thereof to the upper surface of the first region to define a first total fin height. The fin varactor includes a second semiconductor fin that extends from an upper varactor surface thereof to the upper surface of the second region to define a second total fin height that is different from the first total fin height of the finFET.

公开(公告)号：US20180019305A1

公开(公告)日：2018-01-18

申请号：US15717336

申请日：2017-09-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GlobalFoundries, Inc.

Inventor： Kangguo Cheng ,  Xin Miao ,  Ruilong Xie ,  Tenko Yamashita

IPC: H01L29/06 ,  H01L21/02 ,  H01L29/775 ,  H01L29/66 ,  H01L21/265 ,  H01L27/12 ,  H01L27/092 ,  H01L21/84 ,  H01L21/8238 ,  H01L29/786 ,  H01L29/423

CPC classification number: H01L29/0673 ,  B82Y10/00 ,  H01L21/02236 ,  H01L21/02238 ,  H01L21/02252 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/26566 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/78606 ,  H01L29/78618 ,  H01L29/78654 ,  H01L29/78684 ,  H01L29/78696

Abstract: A method of making a nanowire device incudes disposing a first nanowire stack over a substrate, the first nanowire stack including alternating layers of a first and second semiconducting material, the first semiconducting material contacting the substrate and the second semiconducting material being an exposed surface; disposing a second nanowire stack over the substrate, the second nanowire stack including alternating layers of the first and second semiconducting materials, the first semiconducting material contacting the substrate and the second semiconducting material being an exposed surface; forming a first gate spacer along a sidewall of a first gate region on the first nanowire stack and a second gate spacer along a sidewall of a second gate region on the second nanowire stack; oxidizing a portion of the first nanowire stack within the first gate spacer; and removing the first semiconducting material from the first nanowire stack and the second nanowire stack.

公开(公告)号：US20170373005A1

公开(公告)日：2017-12-28

申请号：US15189432

申请日：2016-06-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chengwen Pei ,  Kangguo Cheng ,  Juntao Li ,  Geng Wang

IPC: H01L23/525 ,  H01L29/06 ,  H01L21/265 ,  H01L27/112 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L23/5252 ,  H01L21/265 ,  H01L27/11206 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/785

Abstract: Device structures for an anti-fuse and methods for manufacturing device structures for an anti-fuse. The anti-fuse includes a first terminal comprised of a fin. The fin includes a section with an edge and inclined surfaces that intersect at the edge. The anti-fuse further includes a second terminal covering the edge and the inclined surfaces of the fin, and an isolation dielectric layer on the inclined surfaces and the edge of the fin. The second terminal is separated from the edge and inclined surfaces of the fin by the isolation dielectric layer. The edge and inclined surfaces on the firm may be formed by oxidizing an upper section of the fin in a trench to form an oxide layer, and then removing the oxide layer to expose the edge and inclined surfaces.