公开(公告)号：US20190148373A1

公开(公告)日：2019-05-16

申请号：US15811961

申请日：2017-11-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yongiun Shi ,  Lei Sun ,  Laertis Economikos ,  Ruilong Xie ,  Lars Liebmann ,  Chanro Park ,  Daniel Chanemougame ,  Min Gyu Sung ,  Hsien-Ching Lo ,  Haiting Wang

IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/308 ,  H01L21/762 ,  H01L21/311 ,  H01L29/66 ,  H01L29/06 ,  H01L27/02

CPC classification number: H01L27/0886 ,  H01L21/0276 ,  H01L21/3086 ,  H01L21/31053 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0207 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/6656

Abstract: The disclosure provides integrated circuit (IC) structures with single diffusion break (SDB) abutting end isolation regions, and methods of forming the same. An IC structure may include: a plurality of fins positioned on a substrate; a plurality of gate structures each positioned on the plurality of fins and extending transversely across the plurality of fins; an insulator region positioned on the plurality of fins and laterally between the plurality of gate structures; at least one single diffusion break (SDB) positioned within the insulator region and one of the plurality of fins, the at least one SDB region extending from an upper surface of the substrate to an upper surface of the insulator region; and an end isolation region abutting a lateral end of the at least one SDB along a length of the plurality of gate structures, the end isolation region extending substantially in parallel with the plurality of fins.

公开(公告)号：US20190074224A1

公开(公告)日：2019-03-07

申请号：US15695229

申请日：2017-09-05

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Julien Frougier ,  Min Gyu Sung ,  Edward Joseph Nowak ,  Nigel G. Cave ,  Lars Liebmann ,  Daniel Chanemougame ,  Andreas Knorr

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66

Abstract: The disclosure is directed to gate all-around integrated circuit structures, finFETs having a dielectric isolation, and methods of forming the same. The gate all-around integrated circuit structure may include a first insulator region within a substrate; a pair of remnant liner stubs disposed within the first insulator region; a second insulator region laterally adjacent to the first insulator region within the substrate; a pair of fins over the first insulator region, each fin in the pair of fins including an inner sidewall facing the inner sidewall of an adjacent fin in the pair of fins and an outer sidewall opposite the inner sidewall; and a gate structure substantially surrounding an axial portion of the pair of fins and at least partially disposed over the first and second insulator regions, wherein each remnant liner stub is substantially aligned with the inner sidewall of a respective fin of the pair of fins.

公开(公告)号：US20190035938A1

公开(公告)日：2019-01-31

申请号：US15662526

申请日：2017-07-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chanro Park ,  Steven Bentley ,  Ruilong Xie ,  Min Gyu Sung

IPC: H01L29/786 ,  H01L21/84 ,  H01L27/12 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: Forming a vertical FinFET includes forming a semiconductor fin on a substrate and having a fin mask on an upper surface thereof; laterally recessing the semiconductor fin causing the fin mask; forming a conformal gate liner on the recessed semiconductor fin and the fin mask, wherein the conformal gate liner includes a first portion surrounding the fin mask and a second portion surrounding the recessed fins and being separated from the fin mask by a thickness of the conformal gate liner; forming a gate mask laterally adjacent to the second portion of the conformal gate liner; removing the first portion of the conformal gate liner; removing the gate mask to expose a remaining second portion of the conformal gate liner; and forming a gate contact to the second portion of the conformal gate liner, the remaining second portion of the conformal gate liner defines the gate length.

公开(公告)号：US10177241B2

公开(公告)日：2019-01-08

申请号：US15337254

申请日：2016-10-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chanro Park ,  Ruilong Xie ,  Hoon Kim ,  Min Gyu Sung

IPC: H01L29/66 ,  H01L29/40 ,  H01L21/28 ,  H01L21/3213

Abstract: One illustrative method disclosed includes, among other things, removing a portion of an initial gate cap layer and a portion of an initial sidewall spacer so as to thereby define a gate contact cavity that exposes a portion of a gate structure, completely forming a conductive gate contact structure (CB) in a gate contact cavity, wherein the entire conductive gate contact structure (CB) is positioned vertically above the active region. The method also comprises removing the remaining portion of the initial gate cap layer and to recess a vertical height of exposed portions of the initial sidewall spacer to thereby define a recessed sidewall spacer and a gate cap cavity and forming a replacement gate cap layer in the gate cap cavity so as to define an air space between an upper surface of the recessed sidewall spacer and a lower surface of the replacement gate cap layer.

公开(公告)号：US10170484B1

公开(公告)日：2019-01-01

申请号：US15787009

申请日：2017-10-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Min Gyu Sung ,  Ruilong Xie ,  Bipul C. Paul

IPC: H01L21/00 ,  H01L27/11 ,  H01L29/66 ,  H01L27/088 ,  H01L29/10 ,  H01L29/417 ,  H01L29/78

Abstract: In a method of forming a structure with field effect transistors (FETs) having different drive currents, a stack is formed on a substrate. The substrate is a first semiconductor material and the stack includes alternating layers of a second and the first semiconductor material. Recess(es) filled with sacrificial material are formed in certain area(s) of the stack. The stack is patterned into fins and gate-all-around (GAA) FET processing is performed. GAAFET processing includes removing sacrificial gates to form gate openings for GAAFETs and removing the second semiconductor material and any sacrificial material (if present) from the gate openings such that, within each gate opening, nanoshape(s) that extend laterally between source/drain regions remain. Gate openings for GAAFETs where sacrificial material was removed will have fewer nanoshapes than other gate openings. Thus, in the structure, some GAAFETs will have fewer channel regions and, thereby lower drive currents than others.

公开(公告)号：US20180226402A1

公开(公告)日：2018-08-09

申请号：US15427403

申请日：2017-02-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Min Gyu Sung ,  Kwan-Yong Lim

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/311

CPC classification number: H01L27/0886 ,  H01L21/762 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823481 ,  H01L21/823487 ,  H01L29/0649 ,  H01L29/7827

Abstract: Structures for the integration of a vertical field-effect transistor and a saddle fin-type field-effect transistor into an integrated circuit, as well as methods of integrating a vertical field-effect transistor and a saddle fin-type field-effect transistor into an integrated circuit. A trench isolation is formed in a substrate that defines a first device region and a second device region. A first semiconductor fin is formed that projects from the first device region and a second semiconductor fin is formed that projects from the second device region. A vertical field-effect transistor is formed using the first semiconductor fin, and a saddle fin-type field-effect transistor is formed using the second semiconductor fin. A top surface of the trench isolation in the second device region adjacent to the second semiconductor fin is recessed relative to the top surface of the trench isolation in the first device region adjacent to the first semiconductor fin.

公开(公告)号：US09966456B1

公开(公告)日：2018-05-08

申请号：US15345644

申请日：2016-11-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chanro Park ,  Steven Bentley ,  Hoon Kim ,  Min Gyu Sung ,  Ruilong Xie

IPC: H01L29/66 ,  H01L21/3213 ,  H01L21/288 ,  H01L21/321

CPC classification number: H01L29/66666 ,  H01L21/288 ,  H01L21/32136 ,  H01L21/823456 ,  H01L21/823487 ,  H01L21/823828 ,  H01L21/823871 ,  H01L21/823885 ,  H01L29/7827

Abstract: One illustrative method of forming a vertical transistor device disclosed herein includes, among other things, forming bottom source/drain (S/D) regions. A plurality of vertically oriented channel semiconductor structures is formed above the bottom source/drain (S/D) regions. A gate insulation layer is formed above the vertically oriented channel semiconductor structures. A conformal layer of conductive gate material is formed above the gate insulation layer. The conformal layer of conductive material is etched to define conductive gate spacers on sidewalls of the vertically oriented channel semiconductor structures. Top source/drain (S/D) regions are formed above the vertically oriented channel semiconductor structures.

公开(公告)号：US09953879B1

公开(公告)日：2018-04-24

申请号：US15284110

申请日：2016-10-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min Gyu Sung ,  Hoon Kim ,  Chanro Park ,  Ruilong Xie

IPC: H01L21/8234 ,  H01L21/762 ,  H01L29/66 ,  H01L21/02 ,  H01L27/092

CPC classification number: H01L21/823481 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/02318 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/845 ,  H01L27/0922 ,  H01L29/1054 ,  H01L29/66795

Abstract: A semiconductor structure includes a strain-relaxed semiconductor substrate, fins on the strain-relaxed semiconductor substrate, the fins each having a bottom inactive region and an exposed top active region. The semiconductor structure further includes a liner layer along sidewalls of the bottom inactive region and adjacent surface areas of the strain-relaxed semiconductor substrate, a densified local fill layer surrounding the bottom inactive regions of the plurality of fins, a densified global fill layer adjacent outer sidewalls of the densified local fill layer, and a hard mask layer separating the densified global fill layer from the substrate and the densified local fill layer, a lack of voids in the densified local fill layer resulting in the bottom inactive regions of the fins being substantially free of oxidation defects. A method to realize the structure is also disclosed, the method preventing oxidation defects in strain-relaxed fins by reducing local gap fill voids.

公开(公告)号：US20180102409A1

公开(公告)日：2018-04-12

申请号：US15833285

申请日：2017-12-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Christopher M. Prindle ,  Min Gyu Sung ,  Tek Po Rinus Lee

IPC: H01L29/06 ,  H01L21/311 ,  H01L29/66 ,  H01L29/78 ,  H01L21/762

CPC classification number: H01L29/0649 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/66795 ,  H01L29/785

Abstract: An integrated circuit product includes a FinFET device, a device isolation region that is positioned around a perimeter of the FinFET device, and an isolation protection layer that is positioned above the device isolation region. The FinFET device includes at least one fin, a gate structure, and a sidewall spacer, the device isolation region includes a first insulating material, and the isolation protection layer includes a material that is different from the first insulating material. A first portion of the isolation protection layer is positioned under a portion of the gate structure and under a portion of the sidewall spacer, wherein a second portion of the isolation protection layer is not positioned under the gate structure and is not positioned under the sidewall spacer, the first portion of the isolation protection layer having a thickness that is greater than a thickness of the second portion.

公开(公告)号：US09911619B1

公开(公告)日：2018-03-06

申请号：US15291446

申请日：2016-10-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Hoon Kim ,  Catherine B. Labelle ,  Lars W. Liebmann ,  Chanro Park ,  Min Gyu Sung

IPC: H01L21/308 ,  H01L21/3065 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L29/66795

Abstract: Methods for a lithographic process used to pattern fins for fin-type field-effect transistors (FinFETs). A first plurality of hardmask sections may be formed, and sacrificial spacers may be formed on vertical sidewalls of the first plurality of hardmask sections. Each of the first plurality of hardmask sections is comprised of a first material. Gaps between the sacrificial spacers are filled with a second material, which is selected to etch selectively to the first material, in order to define a second plurality of hardmask sections each comprised of the second material.