公开(公告)号：US10249746B2

公开(公告)日：2019-04-02

申请号：US15856426

申请日：2017-12-28

Applicant: Infineon Technologies AG

Inventor： Frank Dieter Pfirsch ,  Franz-Josef Niedernostheide ,  Hans-Joachim Schulze ,  Stephan Voss

IPC: H01L23/00 ,  H01L29/739 ,  H01L29/15 ,  H01L29/08 ,  H01L29/861 ,  H01L29/06 ,  H01L29/16 ,  H01L29/20

Abstract: A superjunction bipolar transistor includes an active transistor cell area that includes active transistor cells electrically connected to a first load electrode at a front side of a semiconductor body. A superjunction area overlaps the active transistor cell area and includes a low-resistive region and a reservoir region outside of the low-resistive region. The low-resistive region includes a first superjunction structure with a first vertical extension with respect to a first surface at the front side of the semiconductor body. The reservoir region includes no superjunction structure such that the reservoir region includes the semiconductor body that extends from a region located at the first surface to a drain region.

公开(公告)号：US10134885B2

公开(公告)日：2018-11-20

申请号：US15594269

申请日：2017-05-12

Applicant: Infineon Technologies AG

Inventor： Maria Cotorogea ,  Frank Wolter ,  Hans-Joachim Schulze ,  Franz-Josef Niedernostheide ,  Yvonne Gawlina-Schmidl

IPC: H01L29/66 ,  H01L29/739 ,  H01L29/78 ,  H01L29/10 ,  H01L29/06 ,  H01L29/40 ,  H01L29/08 ,  H01L27/115 ,  H01L27/105 ,  H01L27/11521

Abstract: A semiconductor substrate having a first main surface and a transistor cell includes a drift region, a body region between the drift region and the first main surface, an active trench at the first main surface extending into the drift region, a gate insulating layer at sidewalls and a bottom side of the active trench, a gate conductive layer in the active trench, a source region in the body region, and adjacent to the active trench, a body trench at the first main surface extending into the drift region, the body trench being adjacent to the body region and to the drift region, an insulating layer at sidewalls and at a bottom side of the body trench, the insulating layer being asymmetric with respect to an axis extending perpendicular to the first main surface at a center of the body trench, and a conductive layer in the body trench.

公开(公告)号：US10109624B2

公开(公告)日：2018-10-23

申请号：US15492279

申请日：2017-04-20

Applicant: Infineon Technologies AG

Inventor： Markus Bina ,  Franz-Josef Niedernostheide ,  Alexander Philippou

IPC: H01L27/092 ,  G11C11/412 ,  H03K19/094 ,  H01L27/02 ,  G11C11/40 ,  G02F1/1362 ,  H01L21/306 ,  H01L27/082 ,  H03K17/567

Abstract: An embodiment of a semiconductor device comprises a transistor cell array in a semiconductor body. The transistor cell array comprises transistor cell units. Each of the transistor cell units comprises a control terminal and first and second load terminals, respectively. The transistor cell units are electrically connected in parallel, and the control terminals of the transistor cells units are electrically connected. A first group of the transistor cell units includes a first threshold voltage. A second group of the transistor cell units includes a second threshold voltage larger than the first threshold voltage. A channel width of a transistor cell unit of the first group is smaller than a channel width of a transistor cell unit of the second group.

公开(公告)号：US09997517B2

公开(公告)日：2018-06-12

申请号：US15635987

申请日：2017-06-28

Applicant: Infineon Technologies AG

Inventor： Anton Mauder ,  Franz-Josef Niedernostheide ,  Christian Philipp Sandow

IPC: H01L27/088 ,  H01L29/08 ,  H01L29/10 ,  H01L29/06 ,  H01L29/423 ,  H01L29/32

CPC classification number: H01L27/088 ,  H01L29/0607 ,  H01L29/0619 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/105 ,  H01L29/1095 ,  H01L29/32 ,  H01L29/34 ,  H01L29/404 ,  H01L29/4238 ,  H01L29/7397

Abstract: A power semiconductor device is disclosed. In one example, the device includes a semiconductor body coupled to a first load terminal structure and a second load terminal structure. An active cell field is implemented in the semiconductor body. The active cell field is surrounded by an edge termination zone. A plurality of first cells and a plurality of second cells are provided in the active cell field. Each first cell includes a first mesa, the first mesa including: a first port region and a first channel region. Each second cell includes a second mesa, the second mesa including a second port region. The active cell field is surrounded by a drainage region that is arranged between the active cell field and the edge termination zone.

公开(公告)号：US20180006029A1

公开(公告)日：2018-01-04

申请号：US15637170

申请日：2017-06-29

Applicant: Infineon Technologies AG

Inventor： Anton Mauder ,  Franz-Josef Niedernostheide ,  Christian Philipp Sandow

IPC: H01L27/088 ,  H01L29/423 ,  H01L29/10 ,  H03K17/687 ,  H01L29/49 ,  H01L29/739 ,  H01L29/78

CPC classification number: H01L27/0883 ,  H01L29/1037 ,  H01L29/1045 ,  H01L29/4238 ,  H01L29/49 ,  H01L29/7396 ,  H01L29/7802 ,  H03K17/687

Abstract: A power semiconductor device includes a semiconductor body coupled to first and second load terminal structures, and first and second cells each configured for controlling a load current and electrically connected to the first load terminal structure and to a drift region. A first mesa in the first cell includes a port region electrically connected to the first load terminal structure, and a first channel region coupled to the drift region. A second mesa included in the second cell includes a port region electrically connected to the first load terminal structure, and a second channel region coupled to the drift region. The mesas are spatially confined in a direction perpendicular to a direction of the load current by an insulation structure, and have a total extension of less than 100 nm in that direction. The first channel region includes an inversion channel. The second channel region includes an accumulation channel.

公开(公告)号：US09819341B2

公开(公告)日：2017-11-14

申请号：US15223581

申请日：2016-07-29

Applicant: Infineon Technologies AG

Inventor： Christian Philipp Sandow ,  Franz-Josef Niedernostheide

IPC: H03K3/00 ,  H03K17/687 ,  H01L23/48 ,  H01L23/482 ,  H01L23/00 ,  H01L25/18 ,  H01L27/02 ,  H01L29/739 ,  H01L29/74 ,  H01L29/78

CPC classification number: H03K17/687 ,  H01L23/481 ,  H01L23/482 ,  H01L24/05 ,  H01L24/16 ,  H01L25/18 ,  H01L27/0251 ,  H01L27/088 ,  H01L29/7395 ,  H01L29/74 ,  H01L29/7802 ,  H01L29/7827 ,  H01L2224/05025 ,  H01L2224/05568 ,  H01L2224/05571 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16146 ,  H01L2224/16148 ,  H01L2924/014

Abstract: A semiconductor device includes a first transistor cell of a plurality of transistor cells of a vertical field effect transistor arrangement, and a second transistor cell of the plurality of transistor cells. The first transistor cell and the second transistor cell are electrically connected in parallel. A gate of the first transistor cell and a gate of the second transistor cell are controllable by different gate control signals.

公开(公告)号：US20170117397A1

公开(公告)日：2017-04-27

申请号：US15331415

申请日：2016-10-21

Applicant: Infineon Technologies AG

Inventor： Anton Mauder ,  Franz-Josef Niedernostheide ,  Christian Philipp Sandow

IPC: H01L29/739 ,  H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L29/10 ,  H01L29/08

CPC classification number: H01L29/7397 ,  H01L29/0607 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/1033 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7813

Abstract: A power semiconductor transistor includes a semiconductor body coupled to a load terminal, a drift region, a first trench extending into the semiconductor body and including a control electrode electrically insulated from the semiconductor body by an insulator, a source region arranged laterally adjacent to a sidewall of the first trench and electrically connected to the load terminal, a channel region arranged laterally adjacent to the same trench sidewall as the source region, a second trench extending into the semiconductor body, and a guidance zone electrically connected to the load terminal and extending deeper into the semiconductor body than the first trench. The guidance zone is adjacent the opposite sidewall of the first trench as the source region and adjacent one sidewall of the second trench. In a section arranged deeper than the bottom of the first trench, the guidance zone extends laterally towards the channel region.

公开(公告)号：US20170033794A1

公开(公告)日：2017-02-02

申请号：US15223581

申请日：2016-07-29

Applicant: Infineon Technologies AG

Inventor： Christian Philipp Sandow ,  Franz-Josef Niedernostheide

IPC: H03K17/687 ,  H01L23/482 ,  H01L23/48 ,  H01L23/00 ,  H01L25/18 ,  H01L27/02

CPC classification number: H03K17/687 ,  H01L23/481 ,  H01L23/482 ,  H01L24/05 ,  H01L24/16 ,  H01L25/18 ,  H01L27/0251 ,  H01L27/088 ,  H01L29/7395 ,  H01L29/74 ,  H01L29/7802 ,  H01L29/7827 ,  H01L2224/05025 ,  H01L2224/05568 ,  H01L2224/05571 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16146 ,  H01L2224/16148 ,  H01L2924/014

Abstract: A semiconductor device includes a first transistor cell of a plurality of transistor cells of a vertical field effect transistor arrangement, and a second transistor cell of the plurality of transistor cells. The first transistor cell and the second transistor cell are electrically connected in parallel. A gate of the first transistor cell and a gate of the second transistor cell are controllable by different gate control signals.

Abstract translation: 半导体器件包括垂直场效应晶体管布置的多个晶体管单元的第一晶体管单元和多个晶体管单元中的第二晶体管单元。 第一晶体管单元和第二晶体管单元并联电连接。 第一晶体管单元的栅极和第二晶体管单元的栅极可由不同的栅极控制信号控制。

公开(公告)号：US20170025408A1

公开(公告)日：2017-01-26

申请号：US15210449

申请日：2016-07-14

Applicant: Infineon Technologies AG

Inventor： Hans-Joachim Schulze ,  Holger Huesken ,  Franz-Josef Niedernostheide ,  Frank Dieter Pfirsch ,  Roman Roth ,  Christian Philipp Sandow ,  Carsten Schaeffer ,  Stephan Voss

IPC: H01L27/06 ,  H01L29/10 ,  H01L29/739

CPC classification number: H01L27/0664 ,  H01L29/0619 ,  H01L29/0834 ,  H01L29/1095 ,  H01L29/165 ,  H01L29/205 ,  H01L29/45 ,  H01L29/47 ,  H01L29/7397 ,  H01L29/8611 ,  H01L29/8613 ,  H01L29/868 ,  H01L29/872

Abstract: A semiconductor device comprising a source region being electrically connected to a first load terminal (E) of the semiconductor device and a drift region comprising a first semiconductor material (M1) having a first band gap, the drift region having dopants of a first conductivity type and being configured to carry at least a part of a load current between the first load terminal (E) and a second load terminal (C) of the semiconductor device, is presented. The semiconductor device further comprises a semiconductor body region having dopants of a second conductivity type complementary to the first conductivity type and being electrically connected to the first load terminal (E), a transition between the semiconductor body region and the drift region forming a pn-junction, wherein the pn-junction is configured to block a voltage applied between the first load terminal (E) and the second load terminal (C).The semiconductor body region isolates the source region from the drift region and includes a reduced band gap zone comprising a second semiconductor material (M2) having a second band gap that is smaller than the first band gap, wherein the reduced band gap zone is arranged in the semiconductor body region such that the reduced band gap zone and the source region exhibit, in a cross-section along a vertical direction (Z), at least one of a common lateral extension range (LR) along a first lateral direction (X) and a common vertical extension range (VR) along the vertical direction (Z).

Abstract translation: 一种半导体器件，包括电连接到半导体器件的第一负载端子（E）的源极区域和包括具有第一带隙的第一半导体材料（M1）的漂移区域，所述漂移区域具有第一导电类型的掺杂剂 并且被配置为在半导体器件的第一负载端子（E）和第二负载端子（C）之间承载至少一部分负载电流。 半导体器件还包括具有与第一导电类型互补的第二导电类型的掺杂剂并且与第一负载端子（E）电连接的半导体本体区域，在半导体主体区域和漂移区域之间形成pn- 其中所述pn结被配置为阻挡施加在所述第一负载端子（E）和所述第二负载端子（C）之间的电压。所述半导体体区域将所述源极区域与所述漂移区域隔离，并且包括减小的带隙区域 包括具有小于所述第一带隙的第二带隙的第二半导体材料（M2），其中所述还原带隙区域布置在所述半导体主体区域中，使得所述还原带隙区域和所述源极区域在 沿着垂直方向（Z）的横截面，沿着第一横向方向（X）的公共横向延伸范围（LR）和公共垂直伸展中的至少一个 离子范围（VR）沿垂直方向（Z）。

公开(公告)号：US20140034998A1

公开(公告)日：2014-02-06

申请号：US14053631

申请日：2013-10-15

Applicant: Infineon Technologies AG

Inventor： Hans-Joachim Schulze ,  Franz-Josef Niedernostheide ,  Yvonne Gawlina

IPC: H01L29/739 ,  H01L29/78 ,  H01L29/861 ,  H01L29/74

CPC classification number: H01L29/7393 ,  H01L21/263 ,  H01L21/26506 ,  H01L29/0834 ,  H01L29/36 ,  H01L29/66 ,  H01L29/66333 ,  H01L29/66363 ,  H01L29/74 ,  H01L29/7432 ,  H01L29/78 ,  H01L29/861

Abstract: A semiconductor device includes a semiconductor body including a first surface having a normal direction defining a vertical direction, a first n-type semiconductor region arranged below the first surface and having a first maximum doping concentration and a second n-type semiconductor region arranged below the first n-type semiconductor region and including, in a vertical cross-section, two spaced apart first n-type portions each adjoining the first n-type semiconductor region, having a maximum doping concentration which is higher than the first maximum doping concentration and having a first minimum distance to the first surface, and a second n-type portion adjoining the first n-type semiconductor region, having a maximum doping concentration which is higher than the first maximum doping concentration and a second minimum distance to the first surface which is larger than the first minimum distance. A p-type second semiconductor layer forms a pn-junction with the second n-type portion.

Abstract translation: 半导体器件包括半导体本体，其包括具有限定垂直方向的法线方向的第一表面，布置在第一表面下方并具有第一最大掺杂浓度的第一n型半导体区域和布置在第一表面下方的第二n型半导体区域 第一n型半导体区域，并且在垂直截面中包括两个间隔开的第一n型部分，每个邻近第一n型半导体区域的第一n型部分具有高于第一最大掺杂浓度的最大掺杂浓度，并且具有 与第一表面的第一最小距离以及邻接第一n型半导体区域的第二n型部分，其具有高于第一最大掺杂浓度的最大掺杂浓度和第一最小掺杂浓度的第二最小距离， 大于第一最小距离。 p型第二半导体层与第二n型部分形成pn结。