公开(公告)号：US20190280120A1

公开(公告)日：2019-09-12

申请号：US15918800

申请日：2018-03-12

Applicant: International Business Machines Corporation

Inventor： Injo Ok ,  Choonghyun Lee ,  Soon-Cheon Seo ,  Seyoung Kim

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/732 ,  H01L29/08 ,  H01L29/10 ,  H01L29/45 ,  H01L29/66 ,  H01L21/8249 ,  H01L27/06

Abstract: Techniques related to a boosted vertical field effect transistor and method of fabricating the same are provided. A logic device can comprise a vertical field effect transistor comprising a substrate, a first epitaxial layer and a second epitaxial layer. A bottom source/drain contact can be between a top surface and the first epitaxial layer and a top source/drain contact can be between the top surface and the second epitaxial layer at respective first portions of one or more vertical fins. The logic device can also comprise a boosted bipolar junction transistor. A bipolar junction transistor contact can be between the top surface and the second epitaxial layer at respective second portions of the one or more vertical fins. The respective first portions and the respective second portions can be opposite portions of the one or more vertical fins.

公开(公告)号：US20190259854A1

公开(公告)日：2019-08-22

申请号：US16404704

申请日：2019-05-06

Applicant: International Business Machines Corporation

Inventor： Hemanth Jagannathan ,  Choonghyun Lee ,  Alexander Reznicek ,  Christopher Waskiewicz

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06

Abstract: A vertical transport field-effect transistor includes a top source/drain region separated from an underlying gate stack by a top spacer including open gaps to reduce capacitance therebetween. Techniques for fabricating the transistor include using a sacrificial spacer that is selectively removed prior to growth of the top source/drain region. The top source/drain region may be confined by opposing dielectric layers.

公开(公告)号：US10388755B1

公开(公告)日：2019-08-20

申请号：US15996922

申请日：2018-06-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Choonghyun Lee ,  Kangguo Cheng ,  Juntao Li

IPC: H01L21/8234 ,  H01L29/66 ,  H01L21/28 ,  H01L29/78 ,  H01L29/16 ,  H01L29/06 ,  H01L21/285 ,  H01L21/306 ,  H01L21/311 ,  H01L21/02

Abstract: Semiconductor devices and methods of forming the same include forming a stack of alternating channel layers and sacrificial layers. The sacrificial layers are recessed relative to the channel layers. A metal-doped insulator layer is in contact with sidewalls of the channel layers. The metal-doped insulator layer is annealed to form a metallic layer at an interface between the metal-doped insulator layer and the channel layers. The metal-doped insulator layer is etched back to form inner spacers. Source/drain regions are formed in contact with the metallic layer. The sacrificial layers are etched away and a gate stack is formed on and around the channel layers.

公开(公告)号：US10373912B2

公开(公告)日：2019-08-06

申请号：US15862930

申请日：2018-01-05

Applicant: International Business Machines Corporation

Inventor： Choonghyun Lee ,  Chun Wing Yeung ,  Ruqiang Bao ,  Hemanth Jagannathan

IPC: H01L21/8234 ,  H01L23/535 ,  H01L29/786 ,  H01L27/092 ,  H01L29/66 ,  H01L29/423

Abstract: A method of forming a semiconductor structure comprises forming a plurality of fins disposed over a top surface of a substrate and forming one or more vertical transport field-effect transistors (VTFETs) from the plurality of fins using a replacement metal gate (RMG) process. A gate surrounding at least one fin of a given one of the VTFETs comprises a gate self-aligned contact (SAC) capping layer disposed over a gate contact metal layer, the gate contact metal layer being disposed adjacent an end of the at least one fin.

公开(公告)号：US20190229021A1

公开(公告)日：2019-07-25

申请号：US16374114

申请日：2019-04-03

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Pouya Hashemi ,  Choonghyun Lee ,  Alexander Reznicek ,  Jingyun Zhang

IPC: H01L21/8238 ,  H01L27/092

Abstract: A semiconductor device includes a plurality of stacked gate regions spaced apart from each other on a substrate, a plurality of first epitaxial source/drain regions between the plurality of stacked gate regions, wherein the first epitaxial source/drain regions extend from sides of the plurality of stacked gate regions in a first doped region, a plurality of second epitaxial source/drain regions between the plurality of stacked gate regions and positioned over the first epitaxial source/drain regions, wherein the second epitaxial source/drain regions extend from sides of the plurality of stacked gate regions in a second doped region, and a contact region extending through a second epitaxial source/drain region of the plurality of second epitaxial source/drain regions to a first epitaxial source/drain region of the plurality of first epitaxial source/drain regions.

公开(公告)号：US10355103B2

公开(公告)日：2019-07-16

申请号：US15844950

申请日：2017-12-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Robin Hsin Kuo Chao ,  Choonghyun Lee ,  Heng Wu ,  Chun Wing Yeung ,  Jingyun Zhang

IPC: H01L29/66 ,  H01L29/10 ,  H01L21/8234 ,  H01L21/306 ,  H01L29/423

Abstract: A semiconductor device includes a first nanosheet stack, a second nanosheet stack, and a third nanosheet stack arranged on a substrate. The semiconductor device includes a gate arranged on the first nanosheet stack, the second nanosheet stack, and the third nanosheet stack. The semiconductor device includes a channel extending through the gate and from the first nanosheet stack, the second nanosheet stack, and to the third nanosheet stack in a serpentine fashion. The semiconductor device includes a first source/drain and a second source/drain arranged on opposing sides of the gate.

公开(公告)号：US20190214314A1

公开(公告)日：2019-07-11

申请号：US15866851

申请日：2018-01-10

Applicant: International Business Machines Corporation

Inventor： Soon-Cheon Seo ,  Choonghyun Lee ,  Injo Ok

IPC: H01L21/8238 ,  H01L29/66 ,  H01L29/165 ,  H01L27/092 ,  H01L29/06

Abstract: Techniques for source/drain isolation in nanosheet devices are provided. In one aspect, a method of forming a nanosheet device includes: forming an alternating series of sacrificial/active channel nanosheets as a stack on a substrate; forming gates on the stack; forming spacers alongside opposite sidewalls of the gates; patterning the stack, in between the spacers, into individual PFET/NFET stacks and pockets in the substrate; laterally recessing the sacrificial nanosheets in the PFET/NFET stacks to expose tips of the active channel nanosheets in the PFET/NFET stacks; forming inner spacers alongside the PFET/NFET stacks covering the tips of the active channel nanosheets; forming a protective layer lining the pockets; and selectively etching back the inner spacers to expose tips of the active channel nanosheets and epitaxially growing source and drains from the exposed tips of the active channel nanosheets sequentially in the PFET/NFET stacks. A nanosheet device is also provided.

公开(公告)号：US10325820B1

公开(公告)日：2019-06-18

申请号：US15866851

申请日：2018-01-10

Applicant: International Business Machines Corporation

Inventor： Soon-Cheon Seo ,  Choonghyun Lee ,  Injo Ok

IPC: H01L21/70 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/66 ,  H01L29/165 ,  H01L27/092

CPC classification number: H01L21/823878 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0669 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66553

Abstract: Techniques for source/drain isolation in nanosheet devices are provided. In one aspect, a method of forming a nanosheet device includes: forming an alternating series of sacrificial/active channel nanosheets as a stack on a substrate; forming gates on the stack; forming spacers alongside opposite sidewalls of the gates; patterning the stack, in between the spacers, into individual PFET/NFET stacks and pockets in the substrate; laterally recessing the sacrificial nanosheets in the PFET/NFET stacks to expose tips of the active channel nanosheets in the PFET/NFET stacks; forming inner spacers alongside the PFET/NFET stacks covering the tips of the active channel nanosheets; forming a protective layer lining the pockets; and selectively etching back the inner spacers to expose tips of the active channel nanosheets and epitaxially growing source and drains from the exposed tips of the active channel nanosheets sequentially in the PFET/NFET stacks. A nanosheet device is also provided.

公开(公告)号：US20190172924A1

公开(公告)日：2019-06-06

申请号：US16252670

申请日：2019-01-20

Applicant: International Business Machines Corporation

Inventor： Hemanth Jagannathan ,  Choonghyun Lee ,  Alexander Reznicek ,  Christopher Waskiewicz

IPC: H01L29/66 ,  H01L29/06 ,  H01L21/28 ,  H01L29/78

CPC classification number: H01L29/6656 ,  H01L21/28247 ,  H01L29/0653 ,  H01L29/513 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/66666 ,  H01L29/7827

Abstract: A vertical transport field-effect transistor includes a top source/drain region separated from an underlying gate stack by a multi-layer top spacer that includes an oxygen barrier layer beneath a top dielectric layer. Techniques for fabricating the transistor include depositing the oxygen barrier layer over the gate stack prior to depositing the top dielectric layer. The oxygen barrier layer blocks oxygen diffusion during deposition of the top dielectric layer, thereby avoiding damage to underlying interfacial and gate dielectric layers.

公开(公告)号：US10312326B1

公开(公告)日：2019-06-04

申请号：US15844923

申请日：2017-12-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Robin Hsin Kuo Chao ,  Choonghyun Lee ,  Heng Wu ,  Chun Wing Yeung ,  Jingyun Zhang

IPC: H01L29/10 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/285 ,  H01L29/78 ,  H01L21/306

CPC classification number: H01L29/1037 ,  H01L21/28575 ,  H01L21/30604 ,  H01L21/823431 ,  H01L29/66446 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66666 ,  H01L29/66795 ,  H01L29/7827 ,  H01L29/7851

Abstract: A method includes forming a gate on a first fin, a second fin, and a third fin arranged on a substrate. The method includes depositing a semiconductor material on the first fin, the second fin, and the third fin. The method further includes depositing an interlayer dielectric (ILD) on the first fin, the second fin, and the third fin. The method further includes forming a first trench and a second trench through the ILD on a first side of the gate, and a third trench and a fourth trench through the ILD on a second side of the gate, the second trench coupling the second fin to the third fin, and the third trench coupling the first fin to the second fin. The method includes depositing a metal in the first trench, the second trench, the third trench, and the fourth trench.