公开(公告)号：US09634027B2

公开(公告)日：2017-04-25

申请号：US15082180

申请日：2016-03-28

Applicant: International Business Machines Corporation

Inventor： Bruce B. Doris ,  Hong He ,  Ali Khakifirooz ,  Junli Wang

IPC: H01L21/00 ,  H01L23/52 ,  H01L27/12 ,  H01L21/84 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/165 ,  H01L21/02 ,  H01L21/027 ,  H01L21/306 ,  H01L27/092 ,  H01L29/66

CPC classification number: H01L27/1207 ,  H01L21/02532 ,  H01L21/0276 ,  H01L21/30604 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7849

Abstract: A method of forming fins in a complimentary-metal-oxide-semiconductor (CMOS) device that includes a p-type field effect transistor device (pFET) and an n-type field effect transistor (nFET) device and a CMOS device are described. The method includes forming a strained silicon-on-insulator (SSOI) layer in both a pFET region and an nFET region, etching the strained silicon layer, the insulator, and a portion of the bulk substrate in only the pFET region to expose the bulk substrate, epitaxially growing silicon (Si) from the bulk substrate in only the pFET region, and epitaxially growing additional semiconductor material on the Si in only the pFET region. The method also includes forming fins from the additional semiconductor material and a portion of the Si grown on the bulk substrate in the pFET region, and forming fins from the strained silicon layer and the insulator in the nFET region.

公开(公告)号：US09634000B2

公开(公告)日：2017-04-25

申请号：US13831172

申请日：2013-03-14

Applicant: International Business Machines Corporation

Inventor： Hong He ,  Chiahsun Tseng ,  Chun-chen Yeh ,  Yunpeng Yin

IPC: H01L27/088 ,  H01L21/84 ,  H01L21/8234 ,  H01L29/66 ,  H01L27/12

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66477 ,  H01L29/66545

Abstract: A transistor device and a method for forming a fin-shaped field effect transistor (FinFET) device, with the channel portion of the fins on buried silicon oxide, while the source and drain portions of the fins on silicon. An example method includes receiving a wafer with a silicon layer electrically isolated from a silicon substrate by a buried oxide (BOX) layer. The BOX layer is in physical contact with the silicon layer and the silicon substrate. The method further comprises implanting a well in the silicon substrate and forming vertical sources and drains over the well between dummy gates. The vertical sources and drains extend through the BOX layer, fins, and a portion of the dummy gates.

公开(公告)号：US20170092735A1

公开(公告)日：2017-03-30

申请号：US14870936

申请日：2015-09-30

Applicant: International Business Machines Corporation

Inventor： Pouya Hashemi ,  Hong He ,  Alexander Reznicek ,  Tenko Yamashita

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L21/306 ,  H01L21/308

CPC classification number: H01L29/6656 ,  H01L21/30604 ,  H01L21/3081 ,  H01L29/0642 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A replacement gate FinFET manufacturing process in which the source/drain regions, gate structure and gate spacer are all defined by utilizing a single sidewall image transfer technique is provided. In the present application, the source/drain region (i.e., area) are defined by a mandrel structure, while the area for the functional gate structure are defined by the distance between spacers that are located on a pair of neighboring mandrel structures. The gate spacer is defined by the spacer present on the mandrel structures. In some embodiments, semiconductor fin erosion due to gate and gate spacer formation can be reduced or even eliminated.

公开(公告)号：US09583585B2

公开(公告)日：2017-02-28

申请号：US14985711

申请日：2015-12-31

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Hong He ,  Chiahsun Tseng ,  Chun-Chen Yeh ,  Yunpeng Yin

IPC: H01L21/8234 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L29/423 ,  H01L21/033

CPC classification number: H01L29/4966 ,  H01L21/0337 ,  H01L21/823431 ,  H01L29/0847 ,  H01L29/42364 ,  H01L29/42372 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: In one embodiment, a semiconductor device is provided that includes a gate structure present on a channel portion of a fin structure. The gate structure includes a dielectric spacer contacting a sidewall of a gate dielectric and a gate conductor. Epitaxial source and drain regions are present on opposing sidewalls of the fin structure, wherein surfaces of the epitaxial source region and the epitaxial drain region that is in contact with the sidewalls of the fin structure are aligned with an outside surface of the dielectric spacer. In some embodiments, the dielectric spacer, the gate dielectric, and the gate conductor of the semiconductor device are formed using a single photoresist mask replacement gate sequence.

Abstract translation: 在一个实施例中，提供一种半导体器件，其包括存在于鳍结构的沟道部分上的栅极结构。 栅极结构包括与栅极电介质的侧壁和栅极导体接触的电介质间隔物。 外延源极和漏极区域存在于鳍状结构的相对的侧壁上，其中与翅片结构的侧壁接触的外延源区域和外延漏极区域的表面与电介质间隔物的外表面对齐。 在一些实施例中，使用单个光致抗蚀剂掩模替换栅极序列形成半导体器件的电介质间隔物，栅极电介质和栅极导体。

公开(公告)号：US20170054024A1

公开(公告)日：2017-02-23

申请号：US14984215

申请日：2015-12-30

Applicant: International Business Machines Corporation

Inventor： Bruce B. Doris ,  Hong He ,  Sivananda K. Kanakasabapathy ,  Gauri Karve ,  Fee Li Lie ,  Stuart A. Sieg

IPC: H01L29/78 ,  H01L29/165 ,  H01L29/06 ,  H01L29/161

CPC classification number: H01L21/845 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/26506 ,  H01L21/30604 ,  H01L21/76213 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7846 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: A method for forming a fin on a substrate comprises patterning and etching a layer of a first semiconductor material to define a strained fin, depositing a layer of a second semiconductor material over the fin, the second semiconductor material operative to maintain the a strain in the strained fin, etching to remove a portion of the second semiconductor material to define a cavity that exposes a portion of the fin, etching to remove the exposed portion of the fin such that the fin is divided into a first segment and a second segment, and depositing an insulator material in the cavity, the insulator material contacting the first segment of the fin and the second segment of the fin.

公开(公告)号：US20170053942A1

公开(公告)日：2017-02-23

申请号：US14833356

申请日：2015-08-24

Applicant: International Business Machines Corporation

Inventor： Bruce B. Doris ,  Hong He ,  Sivananda K. Kanakasabapathy ,  Gauri Karve ,  Fee Li Lie ,  Stuart A. Sieg

IPC: H01L27/12 ,  H01L29/16 ,  H01L29/06 ,  H01L29/161 ,  H01L29/78

CPC classification number: H01L21/845 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/26506 ,  H01L21/30604 ,  H01L21/76213 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7846 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: A method for forming a fin on a substrate comprises patterning and etching a layer of a first semiconductor material to define a strained fin, depositing a layer of a second semiconductor material over the fin, the second semiconductor material operative to maintain the a strain in the strained fin, etching to remove a portion of the second semiconductor material to define a cavity that exposes a portion of the fin, etching to remove the exposed portion of the fin such that the fin is divided into a first segment and a second segment, and depositing an insulator material in the cavity, the insulator material contacting the first segment of the fin and the second segment of the fin.

公开(公告)号：US20160351590A1

公开(公告)日：2016-12-01

申请号：US14722237

申请日：2015-05-27

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Hong He ,  Sivananda K. Kanakasabapathy ,  Gauri Karve ,  Juntao Li ,  Fee Li Lie ,  Derrick Liu ,  Chun Wing Yeung

IPC: H01L27/12 ,  H01L21/308 ,  H01L21/84 ,  H01L29/78 ,  H01L29/161 ,  H01L29/66

CPC classification number: H01L27/1211 ,  H01L21/845 ,  H01L29/161 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7849

Abstract: A semiconductor structure includes a first strained fin portion and a second strained fin portion, a pair of inactive inner gate structures upon respective strained fin portions, and spacers upon outer sidewalls surfaces of the inactive inner gate structures, upon the inner sidewall surfaces of the inactive inner gate structures, and upon the first strained fin portion and the second strained fin portion end surfaces. The first strained fin portion and the second strained fin portion end surfaces are coplanar with respective inner sidewall surfaces of the inactive inner gate structures. The spacer formed upon the end surfaces limits relaxation of the first strained fin portion and the second strained fin portion and limits shorting between the first strained fin portion and the second strained fin portion.

Abstract translation: 半导体结构包括第一应变翅片部分和第二应变翅片部分，在相应的应变翅片部分上的一对无效内部门结构，以及在非活性内部门结构的外侧壁表面上的间隔物， 内门结构，以及在第一应变翅片部分和第二应变翅片部分端表面上。 第一应变翅片部分和第二应变翅片部分端面与非活性内部门结构的相应的内侧壁表面共面。 形成在端面上的间隔限制了第一应变翅片部分和第二应变翅片部分的松弛，并且限制了第一应变翅片部分和第二应变翅片部分之间的短路。

公开(公告)号：US20160336347A1

公开(公告)日：2016-11-17

申请号：US14712072

申请日：2015-05-14

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Hong He ,  Sivananda K. Kanakasabapathy ,  Chiahsun Tseng ,  Yunpeng Yin

IPC: H01L27/12 ,  H01L21/762 ,  H01L21/02 ,  H01L29/66 ,  H01L21/308 ,  H01L21/3065 ,  H01L21/84 ,  H01L21/311

CPC classification number: H01L27/0886 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76202 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/6656

Abstract: Fabricating a semiconductor device includes providing a substrate, wherein the substrate is comprised of a base layer, a doped silicon layer on top of the base layer, and an undoped silicon layer on top of the doped silicon layer; forming a hard mask layer on top of the substrate; forming at least one mandrel on top of the hard mask layer; forming a spacer layer on top of exposed portions of the hard mask layer and the at least one mandrel; etching portions of the spacer layer; removing the at least one mandrel; etching regions of the hard mask layer and the undoped silicon layer not protected by remaining portions of the spacer layer to form at least one fin; and removing the remaining portions of the spacer layer.

Abstract translation: 制造半导体器件包括提供衬底，其中衬底由基底层，基底层顶部的掺杂硅层和掺杂硅层顶部的未掺杂硅层构成; 在所述基板的顶部上形成硬掩模层; 在所述硬掩模层的顶部上形成至少一个心轴; 在所述硬掩模层和所述至少一个心轴的暴露部分的顶部上形成间隔层; 蚀刻间隔层的部分; 移除所述至少一个心轴; 蚀刻所述硬掩模层和未掺杂的硅层的区域，而不被所述间隔层的剩余部分保护以形成至少一个鳍; 并去除间隔层的剩余部分。

公开(公告)号：US20160315175A1

公开(公告)日：2016-10-27

申请号：US14984445

申请日：2015-12-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Hong He ,  Juntao Li ,  Chih-Chao Yang ,  Yunpeng Yin

IPC: H01L29/66 ,  H01L21/324 ,  H01L21/768 ,  H01L21/3065

CPC classification number: H01L29/66795 ,  H01L21/3065 ,  H01L21/324 ,  H01L21/76897 ,  H01L21/845 ,  H01L23/5256 ,  H01L27/1211 ,  H01L29/66545 ,  H01L29/785

Abstract: An e-Fuse structure is provided on a surface of an insulator layer of a semiconductor-on-insulator substrate (SOI). The e-Fuse structure includes a first metal semiconductor alloy structure of a first thickness, a second metal semiconductor alloy structure of the first thickness, and a metal semiconductor alloy fuse link is located laterally between and connected to the first and second metal semiconductor alloy structures. The metal semiconductor alloy fuse link has a second thickness that is less than the first thickness.

公开(公告)号：US09472621B1

公开(公告)日：2016-10-18

申请号：US14955738

申请日：2015-12-01

Applicant: International Business Machines Corporation

Inventor： Bruce B. Doris ,  Hong He ,  Ali Khakifirooz ,  Joshua M. Rubin

IPC: H01L21/84 ,  H01L31/18 ,  H01L27/12 ,  H01L29/10 ,  H01L21/02 ,  H01L21/311 ,  H01L21/324 ,  H01L29/66

CPC classification number: H01L29/1054 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02271 ,  H01L21/0254 ,  H01L21/02614 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/32105 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/84 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66795

Abstract: A method of forming CMOS structures with selective tensile strained NFET fins and relaxed PFET fins includes performing a first, partial fin etch on a tensile strained silicon layer of a semiconductor substrate; selectively oxidizing bottom surfaces of the tensile strained silicon layer in a PFET region of the semiconductor substrate, thereby causing PFET silicon fins defined in the PFET region to become relaxed; and performing a second fin etch to define NFET silicon fins in an NFET region of the semiconductor substrate, wherein the NFET silicon fins remain tensile strained.

Abstract translation: 一种形成具有选择性拉伸应变NFET鳍片和弛豫PFET鳍片的CMOS结构的方法包括在半导体衬底的拉伸应变硅层上执行第一部分鳍片蚀刻; 选择性地氧化半导体衬底的PFET区域中的拉伸应变硅层的底表面，从而使在PFET区域中限定的PFET硅翅片变得松弛; 以及执行第二鳍蚀刻以在所述半导体衬底的NFET区域中限定NFET硅散热片，其中所述NFET硅散热片保持拉伸应变。