公开(公告)号：US06458703B2

公开(公告)日：2002-10-01

申请号：US09389515

申请日：1999-09-03

申请人： Mamoru Endo ,  Junichi Takeuchi ,  Michio Asahina ,  Eiji Suzuki ,  Kazuki Matsumoto

发明人： Mamoru Endo ,  Junichi Takeuchi ,  Michio Asahina ,  Eiji Suzuki ,  Kazuki Matsumoto

IPC分类号： H01L2144

CPC分类号： H01L21/76856 ,  H01L21/28518 ,  H01L21/76828 ,  H01L21/76843 ,  H01L21/76877

摘要： A method for manufacturing a semiconductor device that fills contact holes with conductive material such as aluminum or an aluminum alloy. A semiconductor device is manufactured by the process of forming an opening such as a contact hole in an interlayer dielectric film formed on a semiconductor substrate having a device element formed thereon. A first film and a second film made of conductive material such as aluminum or an alloy containing aluminum are formed on the interlayer dielectric film and the opening. The second film is then gradually cooled.

摘要翻译： 一种半导体器件的制造方法，其用诸如铝或铝合金的导电材料填充接触孔。 通过在其上形成有器件元件的半导体衬底上形成的层间电介质膜中形成诸如接触孔的开口的方法来制造半导体器件。 在层间电介质膜和开口上形成由铝或含有铝的合金的导电材料制成的第一膜和第二膜。 然后第二个膜逐渐冷却。

公开(公告)号：US06429493B1

公开(公告)日：2002-08-06

申请号：US09420025

申请日：1999-10-18

申请人： Michio Asahina ,  Eiji Suzuki ,  Kazuki Matsumoto ,  Naohiro Moriya

发明人： Michio Asahina ,  Eiji Suzuki ,  Kazuki Matsumoto ,  Naohiro Moriya

IPC分类号： H01L2348

CPC分类号： H01L21/76846 ,  H01L21/2855 ,  H01L21/76801 ,  H01L21/76819 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76856 ,  H01L21/76864 ,  H01L21/76868 ,  H01L21/76886 ,  H01L23/485 ,  H01L23/53223 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a semiconductor substrate having a device element, an interlayer dielectric layer (silicon oxide layer, BPSG layer) formed on the semiconductor substrate, a through hole defined in the interlayer dielectric layer, a barrier layer formed on surfaces of the interlayer dielectric layer and the through hole, and a wiring layer formed on the barrier layer. The barrier layer includes a first metal oxide layer formed from an oxide of a metal that forms the barrier layer (e.g., a first titanium oxide layer), a metal nitride layer formed from a nitride of the metal that forms the barrier layer (e.g., a titanium nitride layer), and a second metal oxide layer formed from an oxide of the metal that forms the barrier layer (e.g., a second titanium oxide layer). The semiconductor device thus manufactured has a barrier layer of an excellent barrier capability.

摘要翻译： 半导体器件包括具有器件元件的半导体衬底，形成在半导体衬底上的层间绝缘层（氧化硅层，BPSG层），层间绝缘层中限定的通孔，形成在层间电介质的表面上的阻挡层 层和通孔，以及形成在阻挡层上的布线层。 阻挡层包括由形成阻挡层（例如，第一氧化钛层）的金属的氧化物形成的第一金属氧化物层，由形成阻挡层的金属的氮化物形成的金属氮化物层（例如， 氮化钛层）和由形成阻挡层的金属的氧化物形成的第二金属氧化物层（例如，第二氧化钛层）。 由此制造的半导体器件具有优异的阻挡能力的阻挡层。

公开(公告)号：US06326287B1

公开(公告)日：2001-12-04

申请号：US09384210

申请日：1999-08-27

申请人： Michio Asahina ,  Kazuki Matsumoto ,  Eiji Suzuki

发明人： Michio Asahina ,  Kazuki Matsumoto ,  Eiji Suzuki

IPC分类号： H01L2120

CPC分类号： H01L21/76856 ,  H01L21/28518 ,  H01L21/2855 ,  H01L21/31612 ,  H01L21/31625 ,  H01L21/32051 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76828 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76877 ,  H01L23/485 ,  H01L23/53223 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device comprising a semiconductor substrate including an electronic element such as a MOSFET, interlayer dielectric (silicon oxide layer or BPSG layer) formed on the semiconductor substrate, a through-hole formed in the interlayer dielectric, a barrier layer formed on a surface of the interlayer dielectric and on a surface of the through-hole, and a metal wiring layer formed on the barrier layer. The metal wiring layer contains aluminum as its major component and 0.1 wt % to 3 wt % of beryllium. An aluminum alloy can be embedded in the through-hole without creation of any void or breaking of wire, and the semiconductor device is highly resistant to electro-migration.

摘要翻译： 一种半导体器件，包括：半导体衬底，其包括形成在所述半导体衬底上的诸如MOSFET的电子元件，层间电介质（氧化硅层或BPSG层），形成在所述层间电介质中的通孔，形成在所述半导体衬底的表面上的阻挡层 所述层间电介质和所述通孔的表面，以及形成在所述阻挡层上的金属布线层。 金属配线层含有铝作为主要成分，0.1重量％〜3重量％的铍。 铝合金可嵌入通孔中而不产生任何空隙或断线，半导体器件具有很高的抗电迁移能力。

公开(公告)号：US09958806B2

公开(公告)日：2018-05-01

申请号：US15346018

申请日：2016-11-08

申请人： Masato Tsuji ,  Tetsumaru Fujita ,  Yuji Nagatomo ,  Mitsutoshi Kichise ,  Yutaro Kaku ,  Kazuki Matsumoto

发明人： Masato Tsuji ,  Tetsumaru Fujita ,  Yuji Nagatomo ,  Mitsutoshi Kichise ,  Yutaro Kaku ,  Kazuki Matsumoto

IPC分类号： G03G15/08

CPC分类号： G03G15/0812

摘要： A developing device includes a toner bearer to rotate while bearing toner and a toner regulator including a bend on a free end side. The bend is disposed in contact with a surface of the toner bearer and defines a regulation nip to adjust an amount of the toner on the toner bearer. The toner regulator further includes an area having a water contact angle greater than or equal to 70 degrees. The area having the water contact angle includes, at least, a downstream end of the bend in a rotation direction of the toner bearer.

公开(公告)号：US20060119565A1

公开(公告)日：2006-06-08

申请号：US11282650

申请日：2005-11-21

申请人： Kazuki Matsumoto

发明人： Kazuki Matsumoto

IPC分类号： G09G3/36

CPC分类号： G09G3/3406 ,  G09G2320/064

摘要： A lighting device is provided with a number of light sources and a driving circuit. Each of the light sources includes a plurality of light emitting elements which emit respective light having different wavelengths, combines the respective light into white light, and emit the white light onto a flat display panel. The driving circuit periodically drives the light sources in accordance with driving pattern signals each corresponding to the ratio between times for which the light emitting elements emit the respective light, and shifts the phases of the driving pattern signals relative to each other for the light sources.

摘要翻译： 照明装置设置有多个光源和驱动电路。 每个光源包括发射具有不同波长的各种光的多个发光元件，将各个光组合成白光，并将白光发射到平板显示面板上。 驱动电路根据与发光元件发射各光的时间的比例对应的驱动图案信号周期性地驱动光源，并且使驱动图案信号的相位相对于光源偏移。

公开(公告)号：US06812123B2

公开(公告)日：2004-11-02

申请号：US09818743

申请日：2001-03-27

申请人： Kazuki Matsumoto ,  Yukio Morozumi ,  Michio Asahina

发明人： Kazuki Matsumoto ,  Yukio Morozumi ,  Michio Asahina

IPC分类号： H01L2144

CPC分类号： H01L24/48 ,  H01L21/76801 ,  H01L21/76828 ,  H01L21/76829 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/45 ,  H01L2224/02126 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05157 ,  H01L2224/05166 ,  H01L2224/0517 ,  H01L2224/05179 ,  H01L2224/05187 ,  H01L2224/05624 ,  H01L2224/13099 ,  H01L2224/451 ,  H01L2224/48463 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/04941 ,  H01L2924/05341 ,  H01L2924/12043 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/04953 ,  H01L2224/45099 ,  H01L2924/00

摘要： Certain embodiments of the present invention relate to a semiconductor device that has a pad section having an excellent coherency with an interlayer dielectric layer, and a method for manufacturing the same. A semiconductor device 1000 has a pad layer 30A formed over an interlayer dielectric layer 20. The interlayer dielectric layer 20 includes at least a first silicon oxide layer 20b that is formed by a polycondensation reaction of a silicon compound and hydrogen peroxide, and a second silicon oxide layer 20c formed over the first silicon oxide layer and containing an impurity. The pad section 30A includes a wetting layer 32, an alloy layer 34 and a metal wiring layer 37.

摘要翻译： 本发明的某些实施例涉及一种半导体器件，其具有与层间介质层具有优异相干性的焊盘部分及其制造方法。 半导体器件1000具有在层间电介质层20上形成的焊盘层30A。层间绝缘层20至少包括通过硅化合物和过氧化氢的缩聚反应形成的第一氧化硅层20b和第二硅 氧化物层20c形成在第一氧化硅层上并含有杂质。 焊盘部分30A包括润湿层32，合金层34和金属布线层37。

公开(公告)号：US06614119B1

公开(公告)日：2003-09-02

申请号：US09521771

申请日：2000-03-09

申请人： Michio Asahina ,  Junichi Takeuchi ,  Naohiro Moriya ,  Kazuki Matsumoto

发明人： Michio Asahina ,  Junichi Takeuchi ,  Naohiro Moriya ,  Kazuki Matsumoto

IPC分类号： H01L2940

CPC分类号： H01L21/76814 ,  H01L21/28518 ,  H01L21/76801 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76837 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/76876 ,  H01L21/76877

摘要： A semiconductor device having a contact structure that can exhibit superlative step coverage without causing voids or wiring discontinuities, using aluminum or aluminum alloys as a conductive substance for via-holes. A method of fabricating the semiconductor device comprises, for at least one layer of wiring regions above the first wiring region on a semiconductor substrate, the following steps (a) to (f): (a) a step of forming a via-hole in a second interlayer dielectric formed above the first wiring region on a semiconductor substrate; (b) a degassing step for removing gaseous components included within the interlayer dielectric by a heat treatment under reduced pressure and at the substrate temperature of 300° C. to 550° C.; (c) a step of forming a wetting layer on the surface of the interlayer dielectric and the via-hole; (d) a step of cooling the substrate to a temperature of no more than 100° C.; (e) a step of forming a first aluminum layer comprising one of aluminum and an alloy in which aluminum is the main component on the wetting layer at a temperature of no more than 200° C.; and (f) a step of forming a second aluminum layer comprising one of aluminum and an alloy in which aluminum is the main component on the first aluminum layer at a temperature of at least 300° C.

摘要翻译： 一种具有接触结构的半导体器件，其可以显示出最高级的覆盖范围，而不引起空隙或接线不连续性，使用铝或铝合金作为通孔的导电物质。 制造半导体器件的方法包括：对于在半导体衬底上的第一布线区域上方的布线区域中的至少一层的以下步骤（a）至（f）：（a）形成通孔的步骤 形成在半导体衬底上的第一布线区域上方的第二层间电介质; （b）通过减压热处理和基板温度在300℃至550℃下除去层间电介质中包含的气体组分的脱气步骤; （c）在层间电介质和通孔的表面上形成润湿层的步骤; （d）将基板冷却至不超过100℃的温度; （e）在不超过200℃的温度下形成包含铝和合金中的铝的第一铝层的步骤，其中铝是润湿层上的主要成分; 以及（f）在至少300℃的温度下形成第一铝层的步骤，所述第二铝层包括铝和合金之一，其中铝是第一铝层上的主要成分。

公开(公告)号：US6144097A

公开(公告)日：2000-11-07

申请号：US220590

申请日：1998-12-28

申请人： Michio Asahina ,  Junichi Takeuchi ,  Naohiro Moriya ,  Kazuki Matsumoto

发明人： Michio Asahina ,  Junichi Takeuchi ,  Naohiro Moriya ,  Kazuki Matsumoto

IPC分类号： H01L21/28 ,  H01L21/316 ,  H01L21/768 ,  H01L23/485 ,  H01L23/522 ,  H01L23/532 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/76846 ,  H01L21/76843 ,  H01L23/485 ,  H01L23/53223 ,  H01L2924/0002 ,  Y10S438/927

摘要： A semiconductor device comprising a semiconductor substrate including an electronic element, interlayer dielectric (silicon oxide layer and BPSG layer) formed on the semiconductor substrate, a contact hole formed in the interlayer dielectric, a barrier layer formed on the interlayer dielectric and contact hole, and a wiring layer formed on the barrier layer. In the barrier layer, metal oxide (titanium oxide) are scattered in an island-like configuration. The barrier layer is formed by depositing a layer that is used to form the barrier layer and then introducing oxygen into the layer. The step is achieved by depositing a layer for the barrier layer, exposing the layer in oxygen plasma under reduced pressure, and subjecting the layer to the thermal processing, or, alternatively by depositing a layer for the barrier layer and subjecting the layer to thermal processing in an atmosphere of oxygen. The semiconductor device of the present invention has a barrier layer with excellent barrier properties.

摘要翻译： 一种半导体器件，包括形成在半导体衬底上的电子元件，层间电介质（氧化硅层和BPSG层）的半导体衬底，形成在层间电介质中的接触孔，形成在层间电介质和接触孔上的阻挡层，以及 形成在阻挡层上的布线层。 在阻挡层中，金属氧化物（氧化钛）以岛状构造分散。 阻挡层通过沉积用于形成阻挡层然后将氧引入层中的层而形成。 该步骤通过沉积阻挡层的层，在减压下在氧等离子体中暴露层，并对该层进行热处理，或者通过沉积用于阻挡层的层并使该层进行热处理来实现 在氧气氛中。 本发明的半导体装置具有阻隔性优异的阻挡层。

公开(公告)号：US6137176A

公开(公告)日：2000-10-24

申请号：US104403

申请日：1998-06-25

申请人： Yukio Morozumi ,  Michio Asahina ,  Naohiro Moriya ,  Kazuki Matsumoto ,  Eiji Suzuki

发明人： Yukio Morozumi ,  Michio Asahina ,  Naohiro Moriya ,  Kazuki Matsumoto ,  Eiji Suzuki

IPC分类号： H01L21/3105 ,  H01L21/316 ,  H01L21/768 ,  H01L23/485 ,  H01L23/522 ,  H01L23/532 ,  H01L29/78 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/76828 ,  H01L21/02129 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02203 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/31051 ,  H01L21/31625 ,  H01L21/76801 ,  H01L21/76804 ,  H01L21/76814 ,  H01L21/76819 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/76864 ,  H01L21/76877 ,  H01L23/485 ,  H01L23/53223 ,  H01L23/5329 ,  H01L2924/0002

摘要： A process of forming an interlayer dielectric on a semiconductor substrate including an electronic element includes:forming first silicon oxide layer by reacting a silicon compound including hydrogen with hydrogen peroxide using a chemical vapor deposition method;forming a porous second silicon oxide layer by reacting between a compound including an impurity, silicon compounds, and at least one substance selected from oxygen and compounds including oxygen using a chemical vapor deposition method; andannealing at a temperature of 300.degree. C. to 850.degree. C. to make the first and second silicon oxide layers more fine-grained. The first silicon oxide layer is formed at a temperature that is lower than that required of a BPSG film, and it has superior self-flattening characteristics in itself.

摘要翻译： 在包括电子元件的半导体衬底上形成层间电介质的工艺包括：通过化学气相沉积法使包括氢的硅化合物与过氧化氢反应形成第一氧化硅层; 通过使用化学气相沉积法在包括杂质，硅化合物和至少一种选自氧的化合物和包括氧的化合物中的化合物之间反应形成多孔的第二氧化硅层; 并在300℃至850℃的温度下进行退火，以使第一和第二氧化硅层更细粒度。 第一氧化硅层形成在低于BPSG膜所要求的温度下，其本身具有优异的自扁平化特性。

公开(公告)号：US20180364620A1

公开(公告)日：2018-12-20

申请号：US15968014

申请日：2018-05-01

申请人： Tomohiro Kubota ,  Naoki Nakatake ,  Minoru Toyoda ,  Kazuki Matsumoto ,  Kenji Nakamura

发明人： Tomohiro Kubota ,  Naoki Nakatake ,  Minoru Toyoda ,  Kazuki Matsumoto ,  Kenji Nakamura

IPC分类号： G03G15/08

摘要： A developing device is provided which includes: a developing roller in contact with or facing an image hearer; a supply roller to supply toner to the developing roller; a casing; a first conveyer disposed within the casing and above the supply roller to supply toner stored in the developing device to the supply roller, while forming a first conveyance path; a second conveyer disposed within the casing with an upper end thereof positioned below that of the first conveyer, while forming a second conveyance path forming a toner circulation path together with the first conveyance path; a partition wall separating the first conveyance path and the second conveyance path in a longitudinal direction within a range excluding both longitudinal end portions; and a toner supply port, at a ceiling of the casing above the second conveyance path, through which toner is supplied to an inside of the developing device.