公开(公告)号：US20160247570A1

公开(公告)日：2016-08-25

申请号：US14723321

申请日：2015-05-27

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Kuo-Pin Chang ,  Hang-Ting Lue

IPC: G11C16/04 ,  G11C16/08

CPC classification number: G11C16/0483 ,  G11C16/08 ,  H01L27/11582

Abstract: A memory device includes a plurality of strings of memory cells. A plurality of stacks of conductive strips includes first upper strips configured as first string select lines for the strings in the plurality of strings, second upper strips configured as second string select lines for the strings in the plurality of strings, and intermediate strips configured as word lines for the strings in the plurality of strings. The memory device includes control circuitry coupled to the first string select lines and the second string select lines, and configured to select a particular string in the plurality of strings by applying a first turn-on voltage to a first string select line in the first string select lines coupled to the particular string, and a second turn-on voltage to a second string select line in the second string select lines coupled to the particular string.

Abstract translation: 存储器件包括多个存储单元串。 导电条的多个堆叠包括构成为多个串中的串的第一串选择线的第一上带，被配置为多个串中的串的第二串选择线的第二上带，以及配置为字的中间带 用于多个字符串中的字符串的行。 存储器件包括耦合到第一串选择线和第二串选择线的控制电路，并且被配置为通过向第一串中的第一串选择线施加第一导通电压来选择多个串中的特定串 选择耦合到特定串的线，以及第二接通电压到耦合到特定串的第二串选择线中的第二串选择线。

公开(公告)号：US09385203B1

公开(公告)日：2016-07-05

申请号：US14587022

申请日：2014-12-31

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hang-Ting Lue

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/40 ,  H01L29/78 ,  H01L29/423 ,  H01L29/417 ,  H01L27/088

CPC classification number: H01L27/088 ,  H01L29/0692 ,  H01L29/4238 ,  H01L29/66659 ,  H01L29/78

Abstract: A high voltage (HV) semiconductor device is provided, comprising a substrate, a first well having a first conductive type and extending down from a surface of the substrate; a plurality of active devices respectively formed on the substrate, and the adjacent active devices electrically separated from each other by an insulation. One of the active devices comprises a diffusion region doped with impurity of the first conductive type and extending down from a surface of the first well, a ring gate formed in the diffusion region, and a light doping region having a second conductive type and extending down from a surface of the diffusion region. The light doping region is offset from an edge of the insulation.

Abstract translation: 提供了一种高压（HV）半导体器件，包括：衬底，具有第一导电类型并从衬底的表面向下延伸的第一阱; 分别形成在基板上的多个有源器件，并且相邻的有源器件通过绝缘彼此电分离。 有源器件中的一个包括掺杂有第一导电类型的杂质并从第一阱的表面向下延伸的扩散区，形成在扩散区中的环形栅，以及具有第二导电类型并向下延伸的光掺杂区 从扩散区域的表面。 光掺杂区域从绝缘体的边缘偏移。

公开(公告)号：US20160141355A1

公开(公告)日：2016-05-19

申请号：US14541170

申请日：2014-11-14

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hang-Ting Lue

IPC: H01L29/06 ,  H01L27/088

CPC classification number: H01L29/0619 ,  H01L21/823481 ,  H01L21/823493 ,  H01L27/0207 ,  H01L27/088 ,  H01L29/0642 ,  H01L29/0646

Abstract: A semiconductor device is provided, comprising a substrate; a first well having a first conductive type and extending down from a surface of the substrate; a diffusion region doped with impurity of the first conductive type and extending down from a surface of the first well; and a plurality of active devices formed within the diffusion region, and the active devices arranged separately from each other. The active devices are electrically isolated from each other by the diffusion region. The active device is self-isolated by a conductive guarding structure, and the semiconductor device comprising embodied STI-free active devices solves STI edge issues.

Abstract translation: 提供一种半导体器件，包括：衬底; 第一阱具有第一导电类型并从衬底的表面向下延伸; 掺杂有第一导电类型的杂质并从第一阱的表面向下延伸的扩散区; 以及形成在扩散区域内的多个有源器件，并且有源器件彼此分开布置。 有源器件通过扩散区域彼此电隔离。 有源器件由导电保护结构自隔离，并且包括实施的无STI的有源器件的半导体器件解决STI边缘问题。

公开(公告)号：US09305653B1

公开(公告)日：2016-04-05

申请号：US14561630

申请日：2014-12-05

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chih-Chang Hsieh ,  Kuo-Pin Chang ,  Hang-Ting Lue

IPC: G11C16/04 ,  G11C16/14 ,  G11C11/56 ,  G11C16/26 ,  G11C16/24 ,  G11C16/34

CPC classification number: G11C16/3431 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0408 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3459 ,  G11C2211/5621 ,  G11C2211/5648

Abstract: A method of operating a memory array is disclosed. The memory array includes a plurality of memory cells arranged in rows and columns, wherein a plurality of parallel memory strings correspond to respective ones of the columns, and a plurality of word lines are arranged orthogonal to the plurality of memory strings, each word line being connected to gate electrodes of a corresponding one of the rows of memory cells. The method includes performing a program operation that programs all of the memory cells on edge word lines located at opposite edges of the memory array, and that programs selected memory cells between the edge word lines in the memory array according to input data to be stored in the memory array. Each programmed memory cell has a threshold voltage at a program verify (PV) level.

Abstract translation: 公开了一种操作存储器阵列的方法。 存储器阵列包括以行和列排列的多个存储单元，其中多个并行存储器串对应于各个列，并且多个字线被布置为与多个存储器串正交，每个字线为 连接到存储器单元的相应行之一的栅电极。 该方法包括执行对位于存储器阵列的相对边缘的边缘字线上的所有存储单元进行编程的程序操作，并且根据要存储在存储器阵列中的输入数据在存储器阵列中的边缘字线之间编程所选存储单元 内存阵列。 每个编程的存储单元在程序验证（PV）级别具有阈值电压。

公开(公告)号：US20160056168A1

公开(公告)日：2016-02-25

申请号：US14555372

申请日：2014-11-26

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hang-Ting Lue

IPC: H01L27/115 ,  H01L21/28 ,  H01L29/792 ,  G11C16/08 ,  H01L21/768 ,  H01L23/528 ,  G11C16/26 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L27/11582 ,  G11C16/08 ,  G11C16/26 ,  H01L21/28282 ,  H01L21/76838 ,  H01L23/528 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/42352 ,  H01L29/66833 ,  H01L29/7926 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A memory device includes a plurality of stacks of conductive strips, a plurality of word lines over and orthogonal to the plurality of stacks of conductive strips, a plurality of vertical gate columns, and control circuitry. The plurality of word lines is electrically coupled to the plurality of vertical gate columns acting as gates controlling current flow in the plurality of stacks of conductive strips. The plurality of word lines including a first word line and a second word line adjacent to each other. The plurality of vertical gate columns is between the plurality of stacks of conductive strips. The plurality of vertical gate columns includes a first set of vertical gate columns electrically coupled to the first word line and a second set of vertical gate columns electrically coupled to the second word line. The first set of vertical gate columns is staggered relative to the second set of vertical gate columns. The control circuitry controls the plurality of word lines as gates to control current flow in the plurality of stacks of conductive strips, and controls nonvolatile memory operations.

Abstract translation: 存储器件包括多个导电条的堆叠，多个字线在多个导体条的堆叠之上并且正交于多个堆叠的导电条，多个垂直栅极列和控制电路。 多个字线电耦合到多个垂直栅极柱，其用作控制多个导电条的堆叠中的电流的栅极。 多个字线包括彼此相邻的第一字线和第二字线。 多个垂直门柱位于多个导电片叠之间。 多个垂直门列包括电耦合到第一字线的第一组垂直栅极列和电耦合到第二字线的第二组垂直栅极列。 第一组垂直栅极列相对于第二组垂直栅极列交错。 控制电路控制多个字线作为门，以控制导电条的多个堆叠中的电流，并且控制非易失性存储器操作。

公开(公告)号：US09214351B2

公开(公告)日：2015-12-15

申请号：US13970482

申请日：2013-08-19

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yi-Hsuan Hsiao ,  Hang-Ting Lue ,  Wei-Chen Chen

IPC: G11C16/04 ,  H01L21/28 ,  H01L29/792 ,  H01L27/115 ,  G11C16/34 ,  G11C16/10 ,  G11C16/26

CPC classification number: G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3418 ,  H01L21/28282 ,  H01L27/11578 ,  H01L29/7926

Abstract: A 3D memory device includes an improved dual gate memory cell. The improved dual gate memory cell has a channel body with opposing first and second side surfaces, charge storage structures on the first and second side surfaces, and a gate structure overlying the charge storage structures on both the first and second side surfaces. The channel body has a depth between the first and second side surfaces less than a threshold channel body depth, combined with the gate structure which establishes an effective channel length of the cell greater than a threshold length. The combination of the channel body depth and effective channel length are related so that the cell channel body can be fully depleted, and sub-threshold leakage current can be suppressed when the memory cell has a high threshold state under a read bias.

Abstract translation: 3D存储器件包括改进的双栅极存储单元。 改进的双栅极存储单元具有通道体，其具有相对的第一和第二侧表面，第一和第二侧表面上的电荷存储结构以及覆盖第一和第二侧表面上的电荷存储结构的栅极结构。 通道体具有小于阈值通道体深度的第一和第二侧表面之间的深度，与构成该单元的有效通道长度大于阈值长度的栅极结构组合。 通道体深度与有效沟道长度的组合是相关联的，使得单元通道体可以完全耗尽，并且当存储单元在读取偏压下具有高阈值状态时，可以抑制亚阈值泄漏电流。

公开(公告)号：US09099538B2

公开(公告)日：2015-08-04

申请号：US14029305

申请日：2013-09-17

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yen-Hao Shih ,  Hang-Ting Lue

IPC: H01L21/3205 ,  H01L21/768 ,  H01L23/48

CPC classification number: H01L21/76883 ,  H01L21/76895 ,  H01L23/481 ,  H01L27/11206 ,  H01L27/11582 ,  H01L27/249 ,  H01L45/085 ,  H01L45/1226 ,  H01L45/146 ,  H01L45/16 ,  H01L2224/16145

Abstract: Conductors in a 3D circuit that include horizontal lines with a plurality of vertical extensions in high aspect ratio trenches can be formed using a two-step etching procedure. The procedure can comprise providing a substrate having a plurality of spaced-apart stacks; forming a pattern of vertical pillars in a body of conductor material between stacks; and forming a pattern of horizontal lines in the body of conductor material over stacks, the horizontal lines connecting vertical pillars in the pattern of vertical pillars. The body of conductor material can be deposited over the plurality of spaced-apart stacks. A first etch process can be used to form the pattern of vertical pillars. A second etch process can be used to form the pattern of horizontal lines. The conductors can be used as word lines or as bit lines in 3D memory.

Abstract translation: 可以使用两步蚀刻工艺来形成包括在高纵横比沟槽中具有多个垂直延伸部的水平线的3D电路中的导体。 该方法可以包括提供具有多个间隔堆叠的基底; 在堆叠体之间形成导体材料体中的垂直柱状图案; 并且在导体材料体中形成水平线的图案，水平线以垂直柱的图案连接垂直柱。 导体材料的主体可以沉积在多个间隔开的叠层上。 可以使用第一蚀刻工艺来形成垂直柱的图案。 可以使用第二蚀刻工艺来形成水平线的图案。 导体可以用作三维存储器中的字线或位线。

公开(公告)号：US09087825B2

公开(公告)日：2015-07-21

申请号：US14049253

申请日：2013-10-09

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hang-Ting Lue ,  Yi-Hsuan Hsiao

IPC: H01L23/485 ,  H01L27/115 ,  H01L29/423 ,  H01L29/792 ,  H01L23/00

CPC classification number: H01L23/485 ,  H01L24/64 ,  H01L27/11578 ,  H01L29/4234 ,  H01L29/792

Abstract: A semiconductor structure and a method for manufacturing the same are provided. The method comprises following steps. A first silicon-containing conductive material is formed on a substrate. A second silicon-containing conductive material is formed on the first silicon-containing conductive material. The first silicon-containing conductive material and the second silicon-containing conductive material have different dopant conditions. The first silicon-containing conductive material and the second silicon-containing conductive material are thermally oxidized for turning the first silicon-containing conductive material wholly into an insulating oxide structure, and the second silicon-containing conductive material into a silicon-containing conductive structure and an insulating oxide layer.

Abstract translation: 提供半导体结构及其制造方法。 该方法包括以下步骤。 在基板上形成第一含硅导电材料。 在第一含硅导电材料上形成第二含硅导电材料。 第一含硅导电材料和第二含硅导电材料具有不同的掺杂条件。 第一含硅导电材料和第二含硅导电材料被热氧化，以将第一含硅导电材料完全转变成绝缘氧化物结构，第二含硅导电材料变成含硅导电结构， 绝缘氧化物层。

公开(公告)号：US20150123192A1

公开(公告)日：2015-05-07

申请号：US14590273

申请日：2015-01-06

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chun-Hsiung Hung ,  Shin-Jang Shen ,  Hang-Ting Lue

IPC: H01L27/115 ,  H01L21/768

CPC classification number: H01L27/11578 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/10 ,  H01L21/76838 ,  H01L27/1021 ,  H01L27/11582

Abstract: A 3D memory device includes a plurality of ridge-shaped stacks, in the form of multiple strips of conductive material separated by insulating material, arranged as strings which can be coupled through decoding circuits to sense amplifiers. Diodes are connected to the bit line structures at either the string select of common source select ends of the strings. The strips of conductive material have side surfaces on the sides of the ridge-shaped stacks. A plurality of conductive lines arranged as word lines which can be coupled to row decoders, extends orthogonally over the plurality of ridge-shaped stacks. Memory elements lie in a multi-layer array of interface regions at cross-points between side surfaces of the conductive strips on the stacks and the conductive lines.

Abstract translation: 3D存储器件包括多个由绝缘材料隔开的多条导电材料形式的脊状叠层，布置成可以通过解码电路耦合到读出放大器的串。 在字符串的公共源选择端的字符串选择处，二极管连接到位线结构。 导电材料条具有在脊形叠层的侧面上的侧表面。 布置成可以连接到行解码器的字线的多条导线垂直地延伸在多个脊形叠层上。 存储器元件位于叠层和导电线上的导电条的侧表面之间的交叉点处的界面区域的多层阵列。

公开(公告)号：US12254949B2

公开(公告)日：2025-03-18

申请号：US18314153

申请日：2023-05-09

Applicant: MACRONIX International Co., Ltd.

Inventor： Teng-Hao Yeh ,  Hang-Ting Lue ,  Chih-Wei Hu

IPC: G11C7/00 ,  G11C5/06 ,  G11C7/06 ,  G11C16/08 ,  H01L23/00 ,  H01L25/065 ,  H10B41/20 ,  H10B41/40 ,  H10B43/20 ,  H10B43/40 ,  H10B80/00

Abstract: A memory device, such as a three-dimensional AND or NOR flash memory, includes a first chip and a second chip. The first chip has multiple source line switches, multiple bit line switches, multiple page buffers, and multiple sensing amplifiers. The first chip has multiple first pads. The second chip has multiple memory cells to form multiple memory cell blocks. Multiple second pads are on a first surface of the second chip to be respectively coupled to multiple local bit lines and multiple local source lines of the memory cell blocks. Each of the first pads is coupled to the corresponding second pads.