公开(公告)号：US09818463B2

公开(公告)日：2017-11-14

申请号：US15390681

申请日：2016-12-26

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely K. Tsern ,  Brian S. Leibowitz ,  Wayne Frederick Ellis ,  Akash Bansal ,  John Welsford Brooks ,  Kishore Ven Kasamsetty

IPC: G06F12/00 ,  G11C8/18 ,  G11C7/10 ,  G06F13/16 ,  G06F13/42

CPC classification number: G11C8/18 ,  G06F13/161 ,  G06F13/1647 ,  G06F13/1657 ,  G06F13/4234 ,  G11C5/02 ,  G11C5/04 ,  G11C7/10 ,  G11C7/1072 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2254

Abstract: In a multirank memory system in which the clock distribution trees of each rank are permitted to drift over a wide range (e.g., low power memory systems), the fine-interleaving of commands between ranks is facilitated through the use of techniques that cause each addressed rank to properly sample commands intended for that rank, notwithstanding the drift. The ability to perform such “microthreading” provides for substantially enhanced memory capacity without sacrificing the performance of single rank systems. This disclosure provides methods, memory controllers, memory devices and system designs adapted to these ends.

公开(公告)号：US09785500B1

公开(公告)日：2017-10-10

申请号：US15390672

申请日：2016-12-26

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Brian S. Leibowitz

IPC: G06F11/00 ,  H03M13/00 ,  G06F11/10 ,  H03M13/35

CPC classification number: G06F11/1048 ,  G06F11/1044 ,  G06F11/1076 ,  H03M13/356 ,  H03M13/6502

Abstract: A memory controller is operable in an error detection/correction mode in which N syndrome values apply to N data words of a data volume, respectively, but a single parity bit is shared across all N data words of the data volume.

公开(公告)号：US09735791B2

公开(公告)日：2017-08-15

申请号：US15130802

申请日：2016-04-15

Applicant: Rambus Inc.

Inventor： Jared L. Zerbe ,  Brian S. Leibowitz ,  Masum Hossain

IPC: H03L7/16 ,  H03L7/06 ,  H03L7/099 ,  H03K5/00 ,  H03K5/13 ,  H03K3/03 ,  H03K5/14 ,  H03L7/24

CPC classification number: H03L7/16 ,  H03J2200/10 ,  H03K3/0315 ,  H03K5/00006 ,  H03K5/13 ,  H03K5/14 ,  H03L7/06 ,  H03L7/0995 ,  H03L7/24

Abstract: In a first clock frequency multiplier, multiple injection-locked oscillators (ILOs) having spectrally-staggered lock ranges are operated in parallel to effect a collective input frequency range substantially wider than that of a solitary ILO. After each input frequency change, the ILO output clocks may be evaluated according to one or more qualifying criteria to select one of the ILOs as the final clock source. In a second clock frequency multiplier, a flexible-injection-rate injection-locked oscillator locks to super-harmonic, sub-harmonic or at-frequency injection pulses, seamlessly transitioning between the different injection pulse rates to enable a broad input frequency range. The frequency multiplication factor effected by the first and/or second clock frequency multipliers in response to an input clock is determined on the fly and then compared with a programmed (desired) multiplication factor to select between different frequency-divided instances of the frequency-multiplied clock.

公开(公告)号：US09734357B2

公开(公告)日：2017-08-15

申请号：US14989155

申请日：2016-01-06

Applicant: Rambus Inc.

Inventor： Trung Am Diep ,  Pradeep Batra ,  Brian S. Leibowitz ,  Frederick A. Ware

IPC: G06F21/00 ,  G06F21/79 ,  G06F12/14 ,  H04L9/30 ,  G06F12/1009

CPC classification number: G06F21/79 ,  G06F12/1009 ,  G06F12/1408 ,  G06F2212/1052 ,  G06F2221/2107 ,  H04L9/30

Abstract: A memory controller encrypts contents of a page frame based at least in part on a frame key associated with the page frame. The memory controller generates a first encrypted version of the frame key based at least in part on a first process key associated with a first process, wherein the first encrypted version of the frame key is stored in a first memory table associated with the first process. The memory controller generates a second encrypted version of the frame key based at least in part on a second process key associated with a second process, wherein the second encrypted version of the frame key is stored in a second memory table associated with the second process, the first process and the second process sharing access to the page frame using the first encrypted version of the frame key and the second encrypted version of the frame key, respectively.

公开(公告)号：US09425997B2

公开(公告)日：2016-08-23

申请号：US14734426

申请日：2015-06-09

Applicant: Rambus Inc.

Inventor： Jared L. Zerbe ,  Fariborz Assaderaghi ,  Brian S. Leibowitz ,  Hae-Chang Lee ,  Jihong Ren ,  Qi Lin

IPC: H04L25/03

CPC classification number: H04L25/03343 ,  H04L25/03057 ,  H04L25/0307 ,  H04L25/03885 ,  H04L2025/03356 ,  H04L2025/03433 ,  H04L2025/03617

Abstract: A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.

公开(公告)号：US20160188911A1

公开(公告)日：2016-06-30

申请号：US14989155

申请日：2016-01-06

Applicant: Rambus Inc.

Inventor： Trung Am Diep ,  Pradeep Batra ,  Brian S. Leibowitz ,  Frederick A. Ware

IPC: G06F21/79 ,  H04L9/30 ,  G06F12/14

CPC classification number: G06F21/79 ,  G06F12/1009 ,  G06F12/1408 ,  G06F2212/1052 ,  G06F2221/2107 ,  H04L9/30

Abstract: A memory controller encrypts contents of a page frame based at least in part on a frame key associated with the page frame. The memory controller generates a first encrypted version of the frame key based at least in part on a first process key associated with a first process, wherein the first encrypted version of the frame key is stored in a first memory table associated with the first process. The memory controller generates a second encrypted version of the frame key based at least in part on a second process key associated with a second process, wherein the second encrypted version of the frame key is stored in a second memory table associated with the second process, the first process and the second process sharing access to the page frame using the first encrypted version of the frame key and the second encrypted version of the frame key, respectively.

Abstract translation: 存储器控制器至少部分地基于与页面帧相关联的帧密钥来加密页面帧的内容。 所述存储器控制器至少部分地基于与第一进程相关联的第一进程密钥来生成所述帧密钥的第一加密版本，其中所述帧密钥的所述第一加密版本被存储在与所述第一进程相关联的第一存储器表中。 所述存储器控制器至少部分地基于与第二进程相关联的第二进程密钥来生成所述帧密钥的第二加密版本，其中所述帧密钥的所述第二加密版本被存储在与所述第二进程相关联的第二存储器表中， 第一进程和第二进程分别使用帧密钥的第一加密版本和帧密钥的第二加密版本共享对页面帧的访问。

公开(公告)号：US20160124895A1

公开(公告)日：2016-05-05

申请号：US14931652

申请日：2015-11-03

Applicant: Rambus Inc.

Inventor： Yohan U. Frans ,  Hae-Chang Lee ,  Brian S. Leibowitz ,  Simon Li ,  Nhat M. Nguyen

IPC: G06F13/42 ,  G06F13/40 ,  G06F13/38

CPC classification number: G06F13/4286 ,  G06F13/385 ,  G06F13/4068 ,  H04L1/0002 ,  H04L1/0015 ,  H04L1/203 ,  H04L1/205 ,  H04L1/243 ,  H04L5/1446 ,  H04L25/0262 ,  H04L25/0292 ,  Y02D50/10

Abstract: A device includes a transmitter coupled to a node, where the node is to couple to a wired link. The transmitter has a plurality of modes of operation including a calibration mode in which a range of communication data rates over the wired link is determined in accordance with a voltage margin corresponding to the wired link at a predetermined error rate. The range of communication data rates includes a maximum data rate, which can be a non-integer multiple of an initial data rate.

公开(公告)号：US09264055B2

公开(公告)日：2016-02-16

申请号：US14444669

申请日：2014-07-28

Applicant: Rambus Inc.

Inventor： Marko Aleksic ,  Brian S. Leibowitz

IPC: G11C11/00 ,  H03L7/099 ,  H03L7/24

CPC classification number: H03L7/24 ,  H03K5/26 ,  H03K2005/00286 ,  H03L7/081 ,  H03L7/099 ,  H03L7/0995

Abstract: Methods and apparatuses featuring an injection-locked oscillator (ILO) are described. In some embodiments, an ILO can have multiple injection points and a free-running frequency that is capable of being adjusted based on a control signal. In some embodiments, each injection point of an ILO can correspond to a phase tuning range. In some embodiments, a circuit can include circuitry to detect a phase boundary between two adjacent phase tuning ranges. In some embodiments, a circuit can use the detected phase boundary to switch between the two adjacent phase tuning ranges.

Abstract translation: 描述了具有注入锁定振荡器（ILO）的方法和装置。 在一些实施例中，国际劳工组织可以具有多个注入点和能够基于控制信号进行调整的自由运行频率。 在一些实施例中，ILO的每个注入点可以对应于相位调谐范围。 在一些实施例中，电路可以包括用于检测两个相邻相位调谐范围之间的相位边界的电路。 在一些实施例中，电路可以使用所检测的相位边界在两个相邻相位调谐范围之间切换。

公开(公告)号：US08964879B2

公开(公告)日：2015-02-24

申请号：US13937549

申请日：2013-07-09

Applicant: Rambus Inc.

Inventor： Reza Navid ,  Amir Amirkhany ,  Dinesh D. Patil ,  Brian S. Leibowitz

IPC: H04B15/00 ,  H04L1/00

CPC classification number: H04L1/0083 ,  H04L1/0001 ,  H04L1/0002 ,  H04L1/0007

Abstract: Data coding schemes perform level-based and/or transition-based encoding to avoid signaling conditions that create worst case crosstalk during transmission of multi-bit data from one circuit to another circuit via a parallel communication link. The coding schemes disallow certain patterns from being present in the signal levels, signal transitions, or a combination of the signal levels and signal transitions that occur in a subset of the multi-bit data that corresponds to certain physically neighboring wires of the parallel communication link.

Abstract translation: 数据编码方案执行基于电平和/或基于转换的编码，以避免在通过并行通信链路将多位数据从一个电路传输到另一电路时产生最差情况串扰的信令条件。 编码方案不允许某些模式存在于信号电平，信号转换或信号电平和信号转换的组合中，信号电平和信号转换发生在对应于并行通信链路的某些物理相邻电线的多位数据的子集中 。

公开(公告)号：US08923467B2

公开(公告)日：2014-12-30

申请号：US13674812

申请日：2012-11-12

Applicant: Rambus Inc.

Inventor： Hae-Chang Lee ,  Thomas H. Greer, III ,  Jade M. Kizer ,  Brian S. Leibowitz ,  Mark A. Horowitz

IPC: H03D3/24 ,  H04L7/00 ,  H04L7/033 ,  H03L7/093 ,  H03L7/07

CPC classification number: H04L7/0012 ,  H03L7/07 ,  H03L7/0807 ,  H03L7/0814 ,  H03L7/091 ,  H03L7/093 ,  H04L7/0008 ,  H04L7/0331 ,  H04L7/0337

Abstract: A system and method for performing clock and data recovery. The system sets the phase of a recovered clock signal according to at least three estimates of the rate of change of an offset between the frequency of the data transmitter clock and the frequency of a receiver clock.

Abstract translation: 一种用于执行时钟和数据恢复的系统和方法。 根据数据发送器时钟的频率和接收机时钟的频率之间的偏移的变化率的至少三个估计，系统设置恢复的时钟信号的相位。