公开(公告)号：US20190294348A1

公开(公告)日：2019-09-26

申请号：US16372336

申请日：2019-04-01

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Robert E. Palmer ,  John W. Poulton

IPC: G06F3/06 ,  G11C11/406 ,  G06F13/16 ,  G11C7/02 ,  G06Q20/00 ,  G06Q10/00

Abstract: A system includes a memory controller and a memory device having a command interface and a plurality of memory banks, each with a plurality of rows of memory cells. The memory controller transmits an auto-refresh command to the memory device. Responsive to the auto-refresh command, during a first time interval, the memory device performs refresh operations to refresh the memory cells and the command interface of the memory device is placed into a calibration mode for the duration of the first time interval. Concurrently, during at least a portion of the first time interval, the memory controller performs a calibration of the command interface of the memory device. The auto-refresh command may specify an order in which memory banks of the memory device are to be refreshed, such that the memory device sequentially refreshes a respective row in the plurality of memory banks in the specified bank order.

公开(公告)号：US10418089B2

公开(公告)日：2019-09-17

申请号：US15389407

申请日：2016-12-22

Applicant: Rambus Inc.

Inventor： Jared L. Zerbe ,  Frederick A. Ware

IPC: G06F1/04 ,  G06F13/42 ,  G11C11/4076 ,  G11C7/10 ,  G11C7/22 ,  G11C7/04 ,  G11C29/02 ,  H04L7/00

Abstract: A method of operating a memory controller is disclosed. The method includes transmitting data signals to a memory device over each one of at least two parallel data links. A timing signal is sent to the memory device on a first dedicated link. The timing signal has a fixed phase relationship with the data signals. A data strobe signal is driven to the memory device on a second dedicated link. Phase information is received from the memory device. The phase information being generated internal to the memory device and based on a comparison between the timing signal and a version of the data strobe signal internally distributed within the memory device. A phase of the data strobe signal is adjusted relative to the timing signal based on the received phase information.

公开(公告)号：US20190237130A1

公开(公告)日：2019-08-01

申请号：US16261937

申请日：2019-01-30

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Thomas Vogelsang

IPC: G11C11/4093 ,  G11C11/4097 ,  G11C11/4076 ,  G11C11/4094

CPC classification number: G11C11/4093 ,  G11C11/4076 ,  G11C11/4094 ,  G11C11/4097

Abstract: A memory stack comprises at least two memory components. The memory components have a first data link interface and are to transmit signals on a data link coupled to the first data link interface at a first voltage level. A buffer component has a second data link interface coupled to the data link. The buffer component is to receive signals on the second data link interface at the first voltage level. A level shifting latch produces a second voltage level in response to receiving the signals at the second data link interface, where the second voltage level is higher than the first voltage level.

公开(公告)号：US20190220222A1

公开(公告)日：2019-07-18

申请号：US16329051

申请日：2017-07-07

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Torsten Partsch

IPC: G06F3/06 ,  G11C7/10 ,  G11C7/06 ,  G11C7/22 ,  H01L25/065 ,  G06F13/16

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679 ,  G06F13/1668 ,  G06F2213/16 ,  G11C7/06 ,  G11C7/1015 ,  G11C7/1057 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4096 ,  G11C2207/107 ,  G11C2207/2272 ,  G11C2207/2281 ,  G11C2207/229 ,  H01L25/0657 ,  H01L2225/06541

Abstract: First data is read out of a core storage array of a memory component over a first time interval constrained by data output bandwidth of the core storage array. After read out from the core storage array, the first data is output from the memory component over a second time interval that is shorter than the first time interval and that corresponds to a data transfer bandwidth greater than the data output bandwidth of the core storage array.

公开(公告)号：US20190115065A1

公开(公告)日：2019-04-18

申请号：US16101480

申请日：2018-08-12

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  James E. Harris

IPC: G11C11/4093 ,  G11C7/22 ,  G11C5/04 ,  G11C5/06 ,  G11C8/12

Abstract: A memory module with multiple memory devices includes a buffer system that manages communication between a memory controller and the memory devices. Each memory device supports an access mode and a low-power mode, the latter used to save power for devices that are not immediately needed. The module provides granular power management using a chip-select decoder that decodes chip-select signals from the memory controller into power-state signals that determine which of the memory devices are in which of the modes. Devices can thus be brought out of the low-power mode in relatively small numbers, as needed, to limit power consumption.

公开(公告)号：US10210102B2

公开(公告)日：2019-02-19

申请号：US15485115

申请日：2017-04-11

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Frederick A. Ware

IPC: G06F13/16 ,  G06F3/06 ,  G06F12/14 ,  G06F12/02

Abstract: A multi-rank memory system in which calibration operations are performed between a memory controller and one rank of memory while data is transferred between the controller and other ranks of memory. A memory controller performs a calibration operation that calibrates parameters pertaining to transmission of data via a first data bus between the memory controller and a memory device in a first rank of memory. While the controller performs the calibration operation, the controller also transfers data with a memory device in a second rank of memory via a second data bus.

公开(公告)号：US10177749B2

公开(公告)日：2019-01-08

申请号：US15478757

申请日：2017-04-04

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Carl W. Werner

IPC: H03K5/22 ,  H04L25/02 ,  H03K3/38 ,  H03K19/0175 ,  H03K19/195

Abstract: In an integrated-circuit component having a signal transmitter receives a transmitter power supply that cycles periodically between power-off and power-on voltage levels to define a sequence of enable intervals during which the signal transmitter is to output voltage levels corresponding to respective transmit data bits onto an external signaling link. The signal transmitter generates, at the start of each output-enable interval, an initial nonzero voltage having a first polarity across conductors of the external signaling link, and then conditionally transitions the initial nonzero voltage to a second nonzero voltage according to whether the transmit data bit corresponding to the output-enable interval has a predetermined one of two binary states, the second nonzero voltage having a polarity opposite the first polarity.

公开(公告)号：US20180350411A1

公开(公告)日：2018-12-06

申请号：US15779977

申请日：2016-12-01

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Carl W. Werner

IPC: G11C7/04 ,  G11C7/22 ,  G11C29/02 ,  G11C29/50 ,  H01L39/22 ,  G06F1/12 ,  H03K5/15

CPC classification number: G06F1/12 ,  G11C7/04 ,  G11C7/222 ,  G11C29/022 ,  G11C29/023 ,  G11C29/50012 ,  G11C2207/2254 ,  H03K5/15

Abstract: In a chip-to-chip signaling system includes at least one signaling link coupled between first and second ICs, the first IC has an interface coupled to the signaling link and timed by a first interface timing signal. The second IC has an interface coupled to the signaling link and timed by a second interface timing signal that is mesochronous with respect to the first interface timing signal. The second IC further has phase adjustment circuitry that adjusts a phase of the second interface timing signal using a digital counter implemented with Josephson-junction circuit elements.

公开(公告)号：US20180336089A1

公开(公告)日：2018-11-22

申请号：US15963163

申请日：2018-04-26

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Liji Gopalakrishnan

IPC: G06F11/10 ,  G06F3/06

Abstract: A memory system employs an addressing scheme to logically divide rows of memory cells into separate contiguous regions, one for data storage and another for error detection and correction (EDC) codes corresponding to that data. Data and corresponding EDC codes are stored in the same row of the same bank. Accessing data and corresponding EDC code in the same row of the same bank advantageously saves power and avoids bank conflicts. The addressing scheme partitions the memory without requiring the requesting processor to have an understanding of the memory partition.

公开(公告)号：US20180267911A1

公开(公告)日：2018-09-20

申请号：US15761746

申请日：2016-09-09

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Kenneth L. Wright ,  John Eric Linstadt ,  Craig Hampel

IPC: G06F13/16 ,  G06F11/10 ,  G11C29/52 ,  G06F3/06 ,  G06F12/0895 ,  G06F13/28

CPC classification number: G06F13/1678 ,  G06F3/0604 ,  G06F3/0613 ,  G06F3/0619 ,  G06F3/0634 ,  G06F3/0656 ,  G06F3/0673 ,  G06F11/1004 ,  G06F11/1068 ,  G06F12/0868 ,  G06F12/0888 ,  G06F12/0895 ,  G06F13/28 ,  G06F2212/1016 ,  G06F2212/1032 ,  G06F2212/403 ,  G11C7/10 ,  G11C29/52

Abstract: Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, a memory module includes a pin interface for coupling to a bus. The bus has a first width. The module includes at least one storage class memory (SCM) component and at least one DRAM component. The memory module operates in a first mode that utilizes all of the first width, and in a second mode that utilizes less than all of the first width.