公开(公告)号：US11963352B2

公开(公告)日：2024-04-16

申请号：US17362034

申请日：2021-06-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Peter Rabkin ,  Masaaki Higashitani

IPC: H10B43/27 ,  H01L21/02 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H01L29/24 ,  H10B41/27

CPC classification number: H10B43/27 ,  H01L21/02565 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L29/24 ,  H10B41/27 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1067 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A semiconductor structure includes at least one set of vertical field effect transistors embedded within dielectric material layers overlying a substrate. Each vertical field effect transistor includes a bottom electrode, a metal oxide semiconductor vertical transistor channel, a cylindrical gate dielectric, and a top electrode. A three-dimensional NAND memory array can be provided over the first field effect transistors, and can be electrically connected to the vertical field effect transistors via metal interconnect structures. Alternatively, a three-dimensional NAND memory array can be formed on another substrate, which can be bonded to the substrate via metal-to-metal bonding. The vertical field effect transistors can be employed as switches for bit lines, word lines, or other components of the three-dimensional NAND memory array.

公开(公告)号：US11948902B2

公开(公告)日：2024-04-02

申请号：US17370317

申请日：2021-07-08

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Lin Hou ,  Peter Rabkin ,  Adarsh Rajashekhar ,  Raghuveer S. Makala ,  Masaaki Higashitani

IPC: H01L23/00

CPC classification number: H01L24/08 ,  H01L24/03 ,  H01L2224/0225 ,  H01L2224/02255 ,  H01L2224/0226 ,  H01L2224/03452 ,  H01L2224/03614 ,  H01L2224/08146 ,  H01L2924/1431 ,  H01L2924/1438

Abstract: A bonded assembly includes a first semiconductor die containing a first substrate, first semiconductor devices, and first bonding pads laterally surrounded by a first pad-level dielectric layer. The first pad-level dielectric layer includes at least one first encapsulated airgap located between neighboring pairs of first bonding pads and encapsulated by a first dielectric fill material of the first pad-level dielectric layer. The bonded assembly includes a second semiconductor die containing a second substrate, second semiconductor devices, and second bonding pads laterally surrounded by a second pad-level dielectric layer. Each of the second bonding pads is bonded to a respective one of the first bonding pads.

公开(公告)号：US20240096850A1

公开(公告)日：2024-03-21

申请号：US17949069

申请日：2022-09-20

Applicant: SanDisk Technologies LLC

Inventor： Jayavel Pachamuthu ,  Srinivasan Sivaram ,  Masaaki Higashitani

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L25/18

CPC classification number: H01L25/0657 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/48 ,  H01L25/18 ,  H01L25/50 ,  H01L24/16 ,  H01L2224/05026 ,  H01L2224/05083 ,  H01L2224/05166 ,  H01L2224/05186 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/08145 ,  H01L2224/16227 ,  H01L2224/48105 ,  H01L2224/48145 ,  H01L2225/06506 ,  H01L2924/04941

Abstract: An integrated controller, logic circuit and memory array (“CLM”) semiconductor device includes stacked controller, memory array logic circuit and memory array wafers, or individual dies diced therefrom, which together operate as a single, integrated semiconductor flash memory device. The memory array logic circuit dies and/or the memory array dies may be formed with full-thickness plated or filled vias connecting to bond pads on opposed surfaces of the dies. The bond pads of the respective stacked semiconductor dies may be aligned and affixed to each other to electrically and mechanically couple each of the semiconductor dies in the respective wafers together.

公开(公告)号：US11856765B2

公开(公告)日：2023-12-26

申请号：US17317578

申请日：2021-05-11

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Koichi Matsuno ,  Masaaki Higashitani ,  Johann Alsmeier

IPC: H01L27/11582 ,  H10B41/27 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: H10B41/27 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, an array of memory opening fill structures located within an array of memory openings vertically extending through the alternating stack, and a drain-select-level isolation structure vertically extending through drain-select-level electrically conductive layers between two rows of memory opening fill structures. The drain-select-level isolation structure may comprise a low-k dielectric material or an air gap.

公开(公告)号：US11598005B2

公开(公告)日：2023-03-07

申请号：US16868787

申请日：2020-05-07

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Shoichi Murakami ,  Shigeru Nakatsuka ,  Syo Fukata ,  Yusuke Osawa ,  Shigehiro Fujino ,  Masaaki Higashitani

IPC: H01L21/683 ,  C23C16/458 ,  H01L21/02 ,  H01L21/687 ,  H01J37/32 ,  H01L21/033 ,  C23C16/50 ,  C23C16/455

Abstract: A deposition chamber includes a vacuum enclosure, an electrostatic chuck having a flat top surface located within a vacuum enclosure, a lift-and-rotation unit extending through or laterally surrounding the electrostatic chuck at a position that is laterally offset from a vertical axis passing through a geometrical center of the electrostatic chuck, a gas supply manifold configured to provide influx of gas into the vacuum enclosure, and a pumping port connected to the vacuum enclosure.

公开(公告)号：US20230042438A1

公开(公告)日：2023-02-09

申请号：US17396291

申请日：2021-08-06

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Lin Hou ,  Peter Rabkin ,  Yangyin Chen ,  Masaaki Higashitani

IPC: H01L25/065 ,  H01L23/32 ,  H01L23/48 ,  H01L23/00 ,  H01L21/768 ,  H01L25/00

Abstract: A bonded assembly includes a first semiconductor die and a second semiconductor die that are bonded to each other by dielectric-to-dielectric bonding. First conductive via structures vertically extend through the second semiconductor die and a respective subset of the first dielectric material layers in the first semiconductor die, and contact a respective first metal interconnect structure in the first semiconductor die. Second conductive via structures vertically extend through a second substrate and a respective subset of the second dielectric material layers in the second semiconductor die, and contacting a respective second metal interconnect structure in the second semiconductor die. Redistribution metal interconnect structures located over a backside surface of the second substrate electrically connect the first conductive via structures and the second conductive via structures, and provide electrical interconnection between the first semiconductor die and the second semiconductor die.

公开(公告)号：US20220413036A1

公开(公告)日：2022-12-29

申请号：US17360573

申请日：2021-06-28

Applicant: SanDisk Technologies LLC

Inventor： Yusuke Ikawa ,  Tsuyoshi Sendoda ,  Kei Samura ,  Masaaki Higashitani

IPC: G01R31/27 ,  G01R31/3183 ,  G01R31/317 ,  G01R31/3181 ,  G06N3/063

Abstract: To provide more test data during the manufacture of non-volatile memories and other integrated circuits, machine learning is used to generate virtual test values. Virtual test results are interpolated for one set of tests for devices on which the test is not performed based on correlations with other sets of tests. In one example, machine learning determines a correlation study between bad block values determined at die sort and photo-limited yield (PLY) values determined inline during processing. The correlation can be applied to interpolate virtual inline PLY data for all of the memory dies, allowing for more rapid feedback on the processing parameters for manufacturing the memory dies and making the manufacturing process more efficient and accurate. In another set of embodiments, the machine learning is used to extrapolate limited metrology (e.g., critical dimension) test data to all of the memory die through interpolated virtual metrology data values.

公开(公告)号：US11476272B2

公开(公告)日：2022-10-18

申请号：US16227374

申请日：2018-12-20

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Peter Rabkin ,  Masaaki Higashitani

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/11558 ,  H01L27/11519 ,  H01L29/792 ,  H01L29/16

Abstract: Memory stack structures extending through an alternating stack of insulating layers and electrically conductive layers is formed over a substrate. Each memory stack structure includes a memory film and a vertical semiconductor channel. A sacrificial polycrystalline metal layer may be formed on each memory film, and a carbon precursor may be decomposed on a physically exposed surface of the sacrificial polycrystalline metal layer to generate adsorbed carbon atoms. A subset of the adsorbed carbon atoms diffuses through grain boundaries in the polycrystalline e metal layer to an interface with the memory film. The carbon atoms at the interface may be coalesced into at least one graphene layer by an anneal process. The at least one graphene layer functions as a vertical semiconductor channel, which provides a higher mobility than silicon. A metallic drain region may be formed at an upper end of each vertical semiconductor channel.

公开(公告)号：US11362079B2

公开(公告)日：2022-06-14

申请号：US16440183

申请日：2019-06-13

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Chen Wu ,  Peter Rabkin ,  Masaaki Higashitani

IPC: H01L25/18 ,  H01L23/48 ,  H01L23/00 ,  H01L25/00 ,  H01L23/528 ,  H01L21/762 ,  H01L21/304 ,  H01L21/306 ,  H01L21/768 ,  H01L27/11551

Abstract: A method of forming a bonded assembly includes providing a first semiconductor die containing a first substrate, first semiconductor devices, first dielectric material layers overlying the first semiconductor devices, and first metal interconnect structures, providing a second semiconductor die containing a second substrate, second semiconductor devices, second dielectric material layers overlying the second semiconductor devices, and second metal interconnect structures, depositing a manganese layer on a top surface of the first dielectric material layers, disposing the second semiconductor die on the manganese layer such that a surface of the second dielectric material layers contacts the manganese layer, and performing a bonding anneal to bond the first semiconductor die to the second semiconductor die and to convert the manganese layer into a manganese-containing oxide layer, such that the manganese-containing oxide layer is bonded to the first dielectric material layers and the second dielectric material layers.

公开(公告)号：US11355486B2

公开(公告)日：2022-06-07

申请号：US17062988

申请日：2020-10-05

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yuki Mizutani ,  Masaaki Higashitani ,  James Kai

IPC: H01L25/18 ,  H01L27/11556 ,  H01L27/11582 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a carrier substrate. Memory stack structures vertically extend through the alternating stack. Each memory stack structure includes a respective vertical semiconductor channel and a respective memory film. The memory die can be bonded to a logic die containing peripheral circuitry for supporting operations of memory cells within the memory die. A distal end of each of the vertical semiconductor channels is physically exposed by removing the carrier substrate. A source layer is formed directly on the distal end each of the vertical semiconductor channels. A source power supply network can be formed on the backside of the source layer.