公开(公告)号：US20170125440A1

公开(公告)日：2017-05-04

申请号：US15333401

申请日：2016-10-25

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Munehiro KOZUMA ,  Yoshiyuki KUROKAWA

IPC: H01L27/118 ,  H01L29/786 ,  H01L29/24 ,  H01L21/48 ,  H01L23/00 ,  H01L23/544 ,  H01L21/66 ,  H01L23/495 ,  H01L23/31 ,  H01L27/12 ,  H01L21/56

CPC classification number: H01L27/11807 ,  H01L22/14 ,  H01L23/3107 ,  H01L23/544 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/92 ,  H01L27/1207 ,  H01L27/1211 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L28/00 ,  H01L29/24 ,  H01L29/78606 ,  H01L29/7869 ,  H01L2027/11838 ,  H01L2027/11875 ,  H01L2027/11879 ,  H01L2027/1189 ,  H01L2223/54486 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/48247 ,  H01L2224/48463 ,  H01L2224/4847 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/3511 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2924/00

Abstract: To achieve high processing capability, a semiconductor device includes first and second circuits, first to third wirings, and first to fourth transistors. The first circuit is electrically connected to the first wiring and a gate of the first transistor. One of a source and a drain of the first transistor is electrically connected to the second wiring. The other of the source and the drain of the first transistor is electrically connected to a gate of the second transistor. The second circuit is electrically connected to the first wiring and a gate of the third transistor. One of a source and a drain of the third transistor is electrically connected to the third wiring. The other of the source and the drain of the third transistor is electrically connected to a gate of the fourth transistor. One of a source and a drain of the fourth transistor is electrically connected to one of a source and a drain of the second transistor. The other of the source and the drain of the fourth transistor is electrically connected to the other of the source and the drain of the second transistor.

公开(公告)号：US20170085264A1

公开(公告)日：2017-03-23

申请号：US15279594

申请日：2016-09-29

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Munehiro KOZUMA ,  Takayuki IKEDA ,  Yoshiyuki KUROKAWA ,  Takeshi AOKI ,  Yuki OKAMOTO

IPC: H03K19/00 ,  H03K19/177 ,  H03K19/0948

CPC classification number: H03K19/0013 ,  H03K19/0948 ,  H03K19/17728 ,  H03K19/1776

Abstract: A semiconductor device suitable for low-voltage driving. The semiconductor device includes a first transistor, a second transistor, a power supply line, a circuit, and a memory circuit. The first transistor controls electrical continuity between the circuit and the power supply line. The memory circuit stores data for setting a gate potential of the first transistor. The second transistor controls electrical continuity between an output node of the memory circuit and a gate of the first transistor. The second transistor is a transistor with an ultralow off-state current, for example, an oxide semiconductor transistor. In a period for operating the circuit, a first potential is input to the power supply line and the second transistor is turned off. In a period for updating the gate potential of the first transistor, a second potential is input to the power supply line. The second potential is higher than the first potential.

公开(公告)号：US20160315600A1

公开(公告)日：2016-10-27

申请号：US15203910

申请日：2016-07-07

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Munehiro KOZUMA ,  Yoshiyuki KUROKAWA ,  Takayuki IKEDA

IPC: H03K3/012 ,  H03B1/02 ,  H01L27/12 ,  H01L29/786 ,  H01L29/24

CPC classification number: H03K3/012 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L29/24 ,  H01L29/7869 ,  H03B1/02 ,  H03K3/0315 ,  H03L7/0995 ,  H03L7/14 ,  H03L2207/08

Abstract: A low-power voltage controlled oscillator is provided. The voltage controlled oscillator includes (2n+1) first circuit components (n is an integer of one or more). An output terminal of the first circuit component in a k-th stage (k is an integer of one or more and 2n or less) is connected to an input terminal of the first circuit component in a (k+1)-th stage. An output terminal of the first circuit component in a (2n+1)-th stage is connected to an input terminal of the first circuit component in a first stage. One of the first circuit components includes a second circuit component and a third circuit component whose input terminal is connected to an output terminal of the second circuit component. The third circuit component includes a first transistor and a second transistor whose source-drain resistance is controlled in accordance with a signal input to a gate through the first transistor.

公开(公告)号：US20160226490A1

公开(公告)日：2016-08-04

申请号：US15007350

申请日：2016-01-27

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Munehiro KOZUMA ,  Takayuki IKEDA ,  Yoshiyuki KUROKAWA ,  Takeshi AOKI ,  Yuki OKAMOTO

IPC: H03K19/00 ,  H03K19/177 ,  H03K19/0948

CPC classification number: H03K19/0013 ,  H03K19/0948 ,  H03K19/17728 ,  H03K19/1776

Abstract: A semiconductor device suitable for low-voltage driving. The semiconductor device includes a first transistor, a second transistor, a power supply line, a circuit, and a memory circuit. The first transistor controls electrical continuity between the circuit and the power supply line. The memory circuit stores data for setting a gate potential of the first transistor. The second transistor controls electrical continuity between an output node of the memory circuit and a gate of the first transistor. The second transistor is a transistor with an ultralow off-state current, for example, an oxide semiconductor transistor. In a period for operating the circuit, a first potential is input to the power supply line and the second transistor is turned off. In a period for updating the gate potential of the first transistor, a second potential is input to the power supply line. The second potential is higher than the first potential.

Abstract translation: 适用于低压驱动的半导体器件。 半导体器件包括第一晶体管，第二晶体管，电源线，电路和存储器电路。 第一个晶体管控制电路和电源线之间的电气连续性。 存储电路存储用于设置第一晶体管的栅极电位的数据。 第二晶体管控制存储电路的输出节点和第一晶体管的栅极之间的电连续性。 第二晶体管是具有超低截止电流的晶体管，例如氧化物半导体晶体管。 在用于操作电路的时段中，第一电位被输入到电源线并且第二晶体管被截止。 在用于更新第一晶体管的栅极电位的时段中，第二电位被输入到电源线。 第二个潜力高于第一个潜力。

公开(公告)号：US20150357476A1

公开(公告)日：2015-12-10

申请号：US14827809

申请日：2015-08-17

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshiyuki KUROKAWA ,  Takayuki IKEDA ,  Hikaru TAMURA ,  Munehiro KOZUMA ,  Masataka IKEDA ,  Takeshi AOKI

IPC: H01L29/786 ,  H01L31/105 ,  H01L27/146

CPC classification number: H01L27/14616 ,  H01L27/14603 ,  H01L27/14632 ,  H01L27/14636 ,  H01L27/14643 ,  H01L29/7869 ,  H01L31/1055 ,  H04N5/361 ,  H04N5/374 ,  H04N5/378

Abstract: In a CMOS image sensor in which a plurality of pixels is arranged in a matrix, a transistor in which a channel formation region includes an oxide semiconductor is used for each of a charge accumulation control transistor and a reset transistor which are in a pixel portion. After a reset operation of the signal charge accumulation portion is performed in all the pixels arranged in the matrix, a charge accumulation operation by the photodiode is performed in all the pixels, and a read operation of a signal from the pixel is performed per row. Accordingly, an image can be taken without a distortion.

Abstract translation: 在其中多个像素以矩阵形式布置的CMOS图像传感器中，其中沟道形成区域包括氧化物半导体的晶体管被​​用于处于像素部分的电荷累积控制晶体管和复位晶体管。 在矩阵中排列的所有像素中执行信号电荷累积部分的复位操作之后，在所有像素中执行光电二极管的电荷累积操作，并且每行执行来自像素的信号的读取操作。 因此，可以采取没有失真的图像。

公开(公告)号：US20150334321A1

公开(公告)日：2015-11-19

申请号：US14723971

申请日：2015-05-28

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Munehiro KOZUMA

IPC: H04N5/363 ,  H04N5/378

CPC classification number: H04N5/363 ,  G01J1/46 ,  H03F3/08 ,  H04N5/357 ,  H04N5/3745 ,  H04N5/378

Abstract: Adverse effects of noise are reduced. A photodetector circuit, a difference data generation circuit, and a data input selection circuit are included. The photodetector circuit has a function of generating an optical data signal. A first data signal and a second data signal is input to the difference data generation circuit and the difference data generation circuit has a function of generating difference data of data of the first data signal and data of the second data signal. The data input selection circuit has a function of determining that the data of optical data signal is regarded as data of the first data signal or data of the second data signal.

Abstract translation: 噪音的不利影响降低。 包括光电检测器电路，差分数据生成电路和数据输入选择电路。 光检测器电路具有产生光数据信号的功能。 第一数据信号和第二数据信号被输入到差数据生成电路，差数据生成电路具有产生第一数据信号的数据和第二数据信号的数据的差分数据的功能。 数据输入选择电路具有确定光数据信号的数据被认为是第一数据信号的数据或第二数据信号的数据的功能。

公开(公告)号：US20150279896A1

公开(公告)日：2015-10-01

申请号：US14740720

申请日：2015-06-16

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshiyuki KUROKAWA ,  Takayuki IKEDA ,  Hikaru TAMURA ,  Munehiro KOZUMA

IPC: H01L27/146 ,  H01L27/12

CPC classification number: H01L27/14643 ,  G02F1/1362 ,  G02F2001/13312 ,  H01L27/1225 ,  H01L27/14632 ,  H01L27/1464 ,  H04N5/378

Abstract: An object is to achieve low-power consumption by reducing the off-state current of a transistor in a photosensor. A semiconductor device including a photosensor having a photodiode, a first transistor, and a second transistor; and a read control circuit including a read control transistor, in which the photodiode has a function of supplying charge based on incident light to a gate of the first transistor; the first transistor has a function of storing charge supplied to its gate and converting the charge stored into an output signal; the second transistor has a function of controlling reading of the output signal; the read control transistor functions as a resistor converting the output signal into a voltage signal; and semiconductor layers of the first transistor, the second transistor, and the read control transistor are formed using an oxide semiconductor.

Abstract translation: 目的是通过降低光电传感器中的晶体管的截止电流来实现低功耗。 一种半导体器件，包括具有光电二极管的光传感器，第一晶体管和第二晶体管; 以及包括读取控制晶体管的读取控制电路，其中光电二极管具有基于入射光向第一晶体管的栅极提供电荷的功能; 第一晶体管具有存储提供给其栅极的电荷并将存储的电荷转换为输出信号的功能; 第二晶体管具有控制输出信号的读取的功能; 读控制晶体管用作将输出信号转换成电压信号的电阻器; 并且使用氧化物半导体形成第一晶体管，第二晶体管和读控制晶体管的半导体层。

公开(公告)号：US20150256156A1

公开(公告)日：2015-09-10

申请号：US14635117

申请日：2015-03-02

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Munehiro KOZUMA ,  Yoshiyuki KUROKAWA ,  Takayuki IKEDA

IPC: H03K3/012 ,  H03B1/02

CPC classification number: H03K3/012 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L29/24 ,  H01L29/7869 ,  H03B1/02 ,  H03K3/0315 ,  H03L7/0995 ,  H03L7/14 ,  H03L2207/08

Abstract: A low-power voltage controlled oscillator is provided. The voltage controlled oscillator includes (2n+1) first circuit components (n is an integer of one or more). An output terminal of the first circuit component in a k-th stage (k is an integer of one or more and 2n or less) is connected to an input terminal of the first circuit component in a (k+1)-th stage. An output terminal of the first circuit component in a (2n+1)-th stage is connected to an input terminal of the first circuit component in a first stage. One of the first circuit components includes a second circuit component and a third circuit component whose input terminal is connected to an output terminal of the second circuit component. The third circuit component includes a first transistor and a second transistor whose source-drain resistance is controlled in accordance with a signal input to a gate through the first transistor.

Abstract translation: 提供了一个低功耗压控振荡器。 压控振荡器包括（2n + 1）个第一电路部件（n为1以上的整数）。 第k级的第一电路部件的输出端子（k为1以上且2n以下的整数）在第（k + 1）级连接到第一电路部件的输入端子。 第（2n + 1）级中的第一电路部件的输出端在第一级连接到第一电路部件的输入端。 第一电路部件中的一个包括第二电路部件和第三电路部件，其输入端子连接到第二电路部件的输出端子。 第三电路部件包括第一晶体管和第二晶体管，源极 - 漏极电阻根据通过第一晶体管输入到栅极的信号来控制。

公开(公告)号：US20150255157A1

公开(公告)日：2015-09-10

申请号：US14636792

申请日：2015-03-03

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takayuki IKEDA ,  Yoshiyuki KUROKAWA ,  Munehiro KOZUMA

IPC: G11C16/04 ,  G11C16/10

CPC classification number: G11C11/24 ,  G11C7/16 ,  G11C11/40 ,  G11C11/404 ,  G11C11/405 ,  G11C11/4091 ,  G11C16/0441 ,  G11C16/10 ,  G11C27/005 ,  G11C27/02 ,  G11C27/024 ,  H01L21/02565 ,  H01L21/0262 ,  H01L23/528 ,  H01L27/1052 ,  H01L27/1156 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/1255 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78693

Abstract: A semiconductor device capable of generating a signal (e.g., a potential signal or a current signal) suitable for usage environment or a purpose. The semiconductor device includes a first memory circuit, a first circuit, and a second memory circuit. The first circuit converts a digital signal input from the first memory circuit into an analog signal. The first memory circuit includes an input node, an output node, a transistor, and a capacitor. The capacitor is electrically connected to the output node. The transistor can control a conduction state between the input node and the output node. An analog signal is input to the input node from the first circuit. The transistor includes an oxide semiconductor layer where a channel formation region is formed.

Abstract translation: 能够产生适合于使用环境或目的的信号（例如，电位信号或电流信号）的半导体器件。 半导体器件包括第一存储器电路，第一电路和第二存储器电路。 第一电路将从第一存储器电路输入的数字信号转换为模拟信号。 第一存储器电路包括输入节点，输出节点，晶体管和电容器。 电容器电连接到输出节点。 晶体管可以控制输入节点和输出节点之间的导通状态。 模拟信号从第一电路输入到输入节点。 晶体管包括其中形成沟道形成区的氧化物半导体层。

公开(公告)号：US20150228324A1

公开(公告)日：2015-08-13

申请号：US14613554

申请日：2015-02-04

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takeshi AOKI ,  Munehiro KOZUMA

IPC: G11C11/34

CPC classification number: G11C11/34 ,  G06F17/5045 ,  G06F17/5054 ,  H03K19/177 ,  H03K19/1776

Abstract: A low-power semiconductor device is provided. A memory device applicable to a multi-context programmable logic device (PLD) includes at least memory cells the number of which is the same as the number of contexts. Output nodes of the memory cells are electrically connected to an output node of a configuration memory through different path transistors. A circuit including a transistor and a capacitor makes a gate potential of the path transistor higher than a high-level potential. This prevents a decrease in the potential of the output node of the configuration memory due to the threshold voltage of the path transistor without an increase in power consumption.

Abstract translation: 提供了一种低功率半导体器件。 适用于多上下文可编程逻辑器件（PLD）的存储器件至少包括其数量与上下文数量相同的存储器单元。 存储单元的输出节点通过不同的路径晶体管电连接到配置存储器的输出节点。 包括晶体管和电容器的电路使路径晶体管的栅极电位高于高电位电位。 这防止由于路径晶体管的阈值电压而导致的配置存储器的输出节点的电位降低，而不增加功耗。