利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

126 条记录 (耗时 0.047 秒)

    Molecular self-assembly in substrate processing
    81.
    发明授权
    Molecular self-assembly in substrate processing 有权
    基板加工中的分子自组装

    公开(公告)号：US08883633B2

    公开(公告)日：2014-11-11

    申请号：US13074771

    申请日：2011-03-29

    申请人： David E. Lazovsky ,  Tony P. Chiang ,  Majid Keshavarz

    发明人： David E. Lazovsky ,  Tony P. Chiang ,  Majid Keshavarz

    IPC分类号： B05D5/12 ,  H01L21/768 ,  H01L21/31 ,  H01L29/06 ,  B82Y30/00 ,  H01L49/02

    CPC分类号： H01L23/5329 ,  B82Y30/00 ,  H01L21/31 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76873 ,  H01L21/76879 ,  H01L28/65 ,  H01L29/06 ,  H01L2924/0002 ,  Y10T428/249953 ,  H01L2924/00

    摘要： Methods for sealing a porous dielectric are presented including: receiving a substrate, the substrate including the porous dielectric; exposing the substrate to an organosilane, where the organosilane includes a hydrolysable group for facilitating attachment with the porous dielectric, and where the organosilane does not include an alkyl group; and forming a layer as a result of the exposing to seal the porous dielectric. In some embodiments, methods are presented where the organosilane includes: alkynyl groups, aryl groups, flouroalkyl groups, heteroarlyl groups, alcohol groups, thiol groups, amine groups, thiocarbamate groups, ester groups, ether groups, sulfide groups, and nitrile groups. In some embodiments, method further include: removing contamination from the porous dielectric and a conductive region of the substrate prior to the exposing; and removing contamination from the conductive region after the forming.

    摘要翻译： 提供了密封多孔电介质的方法，包括：接收衬底，所述衬底包括多孔电介质; 将基板暴露于有机硅烷中，其中有机硅烷包括用于促进与多孔电介质附着的可水解基团，并且其中有机硅烷不包括烷基; 并且由于暴露而形成层以密封多孔电介质。 在一些实施方案中，存在方法，其中有机硅烷包括：炔基，芳基，氟烷基，杂芳基，醇基，硫醇基，胺基，硫代氨基甲酸酯基，酯基，醚基，硫醚基和腈基。 在一些实施例中，方法还包括：在暴露之前从多孔电介质和衬底的导电区域去除污染物; 并且在成形之后从导电区域去除污染物。

    Nonvolatile resistive memory element with an integrated oxygen isolation structure
    82.
    发明授权
    Nonvolatile resistive memory element with an integrated oxygen isolation structure 有权
    具有集成氧隔离结构的非易失性电阻式存储元件

    公开(公告)号：US08878152B2

    公开(公告)日：2014-11-04

    申请号：US13408103

    申请日：2012-02-29

    申请人： Yun Wang ,  Tony P. Chiang ,  Imran Hashim ,  Dipankar Pramanik

    发明人： Yun Wang ,  Tony P. Chiang ,  Imran Hashim ,  Dipankar Pramanik

    IPC分类号： H01L29/02

    CPC分类号： H01L45/16 ,  H01L27/2463 ,  H01L45/10 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1675

    摘要： A nonvolatile resistive memory element includes one or more novel oxygen isolation structures that protect the resistive switching material of the memory element from oxygen migration. One such oxygen isolation structure comprises an oxygen barrier layer that isolates the resistive switching material from other portions of the resistive memory device during fabrication and/or operation of the memory device. Another such oxygen isolation structure comprises a sacrificial layer that reacts with unwanted oxygen migrating toward the resistive switching material during fabrication and/or operation of the memory device.

    摘要翻译： 非易失性电阻存储元件包括一个或多个新颖的氧隔离结构，其保护存储元件的电阻开关材料免于氧迁移。 一个这样的氧隔离结构包括氧阻隔层，其在制造和/或操作存储器件期间将电阻性开关材料与电阻式存储器件的其它部分隔离。 另一种这样的氧隔离结构包括牺牲层，其在存储器件的制造和/或操作期间与向电阻开关材料迁移的不想要的氧化反应。

    System and method for increasing productivity of combinatorial screening
    84.
    发明授权
    System and method for increasing productivity of combinatorial screening 有权
    提高组合筛选生产力的系统和方法

    公开(公告)号：US08772772B2

    公开(公告)日：2014-07-08

    申请号：US11419174

    申请日：2006-05-18

    申请人： Kurt H. Weiner ,  Tony P. Chiang ,  Gustavo A. Pinto

    发明人： Kurt H. Weiner ,  Tony P. Chiang ,  Gustavo A. Pinto

    IPC分类号： H01L23/58

    CPC分类号： H01L22/10 ,  H01L21/67005 ,  H01L22/34

    摘要： The present invention provides systems and methods for simultaneous, parallel and/or rapid serial testing of material parameters or other parameters of the result of a process. The testing is typically used for screening different methods or materials to select those methods or materials with desired properties. A reactor structure used to form the materials may consist of an array of small isolated reaction chambers that overlie the substrate so that the substrate forms a bottom surface of each isolated reaction chamber. Test structures are formed on the substrate, where the location of each test structure corresponds to an isolated reaction chamber area of the reaction structure. Test structures are used to measure certain parameters, such as by probing contact pads for each test structure, or such testing may be performed in-situ during processing.

    摘要翻译： 本发明提供用于同时，并行和/或快速连续测试材料参数或过程结果的其它参数的系统和方法。 测试通常用于筛选不同的方法或材料以选择具有所需性质的那些方法或材料。 用于形成材料的反应器结构可以由覆盖在基板上的小的分离的反应室的阵列组成，使得基板形成每个分离的反应室的底表面。 在基板上形成测试结构，其中每个测试结构的位置对应于反应结构的分离的反应室区域。 测试结构用于测量某些参数，例如通过探测每个测试结构的接触垫，或者可以在处理期间原位进行这种测试。

    Methods of combinatorial processing for screening multiple samples on a semiconductor substrate
    87.
    发明授权
    Methods of combinatorial processing for screening multiple samples on a semiconductor substrate 失效
    用于在半导体衬底上筛选多个样品的组合处理方法

    公开(公告)号：US08383430B2

    公开(公告)日：2013-02-26

    申请号：US13399719

    申请日：2012-02-17

    申请人： Guarav Verma ,  Tony P. Chiang ,  Imran Hashim ,  Sandra G Malhotra ,  Prashant B Phatak ,  Kurt H Weiner

    发明人： Guarav Verma ,  Tony P. Chiang ,  Imran Hashim ,  Sandra G Malhotra ,  Prashant B Phatak ,  Kurt H Weiner

    IPC分类号： H01L21/00

    CPC分类号： G01R31/2831 ,  G01R31/2834 ,  H01L22/34

    摘要： In embodiments of the current invention, methods of combinatorial processing and a test chip for use in these methods are described. These methods and test chips enable the efficient development of materials, processes, and process sequence integration schemes for semiconductor manufacturing processes. In general, the methods simplify the processing sequence of forming devices or partially formed devices on a test chip such that the devices can be tested immediately after formation. The immediate testing allows for the high throughput testing of varied materials, processes, or process sequences on the test chip. The test chip has multiple site isolated regions where each of the regions is varied from one another and the test chip is designed to enable high throughput testing of the different regions.

    摘要翻译： 在本发明的实施例中，描述了用于这些方法的组合处理方法和测试芯片。 这些方法和测试芯片能够有效地开发用于半导体制造工艺的材料，工艺和工艺顺序集成方案。 通常，这些方法简化了在测试芯片上形成器件或部分形成的器件的处理顺序，使得器件可以在形成后立即进行测试。 即时测试允许测试芯片上各种材料，工艺或工艺顺序的高通量测试。 测试芯片具有多个位置隔离区域，其中每个区域彼此变化，并且测试芯片被设计为能够实现不同区域的高通量测试。

    Molecular self-assembly in substrate processing
    88.
    发明授权
    Molecular self-assembly in substrate processing 有权
    基板加工中的分子自组装

    公开(公告)号：US08372759B2

    公开(公告)日：2013-02-12

    申请号：US13045298

    申请日：2011-03-10

    申请人： David E. Lazovsky ,  Tony P. Chiang ,  Majid Keshavarz

    发明人： David E. Lazovsky ,  Tony P. Chiang ,  Majid Keshavarz

    IPC分类号： H01L21/469

    CPC分类号： H01L23/5329 ,  B82Y30/00 ,  H01L21/31 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76873 ,  H01L21/76879 ,  H01L28/65 ,  H01L29/06 ,  H01L2924/0002 ,  Y10T428/249953 ,  H01L2924/00

    摘要： Methods for sealing a porous dielectric are presented including: receiving a substrate, the substrate including the porous dielectric; exposing the substrate to an organosilane, where the organosilane includes a hydrolysable group for facilitating attachment with the porous dielectric, and where the organosilane does not include an alkyl group; and forming a layer as a result of the exposing to seal the porous dielectric. In some embodiments, methods are presented where the organosilane includes: alkynyl groups, aryl groups, fluoroalkyl groups, heteroaryl groups, alcohol groups, thiol groups, amine groups, thiocarbamate groups, ester groups, ether groups, sulfide groups, and nitrile groups. In some embodiments, method further include: removing contamination from the porous dielectric and a conductive region of the substrate prior to the exposing; and removing contamination from the conductive region after the forming.

    摘要翻译： 提供了密封多孔电介质的方法，包括：接收衬底，所述衬底包括多孔电介质; 将基板暴露于有机硅烷中，其中有机硅烷包括用于促进与多孔电介质附着的可水解基团，并且其中有机硅烷不包括烷基; 并且由于暴露而形成层以密封多孔电介质。 在一些实施方案中，存在方法，其中有机硅烷包括：炔基，芳基，氟代烷基，杂芳基，醇基，硫醇基，胺基，硫代氨基甲酸酯基，酯基，醚基，硫醚基和腈基。 在一些实施例中，方法还包括：在暴露之前从多孔电介质和衬底的导电区域去除污染物; 并且在成形之后从导电区域去除污染物。