-
公开(公告)号：US09812426B1
公开(公告)日：2017-11-07
申请号：US15257920
申请日：2016-09-07
发明人： Chin-Te Wang , Cheng-Hsien Hsieh , Hsien-Wei Chen , Li-Han Hsu , Tzu-Shiun Sheu , Wei-Cheng Wu , Yan-Fu Lin
IPC分类号： H01L25/065 , H01L23/00 , H01L25/00
CPC分类号： H01L25/0657 , H01L24/02 , H01L24/13 , H01L25/16 , H01L25/50 , H01L2224/02166 , H01L2224/02206 , H01L2224/0221 , H01L2224/113 , H01L2224/13018 , H01L2224/13024 , H01L2224/13027 , H01L2225/06513 , H01L2225/06524 , H01L2225/06548 , H01L2225/06586
摘要： A semiconductor device including an integrated circuit, a protection layer, and a conductive via is provided. The integrated circuit includes at least one conductive pad. The protection layer covers the integrated circuit. The protection layer includes a contact opening, and the conductive pad is exposed by the contact opening of the protection layer. The conductive via is embedded in the contact opening of the protection layer, and the conductive via is electrically connected to the conductive pad through the contact opening. A method of fabricating the above-mentioned semiconductor device and an integrated fan-out package including the above-mentioned semiconductor device are also provided.
-
公开(公告)号：US20170278802A1
公开(公告)日：2017-09-28
申请号：US15162630
申请日：2016-05-24
发明人： Shao-Yun Chen , Hsien-Wei Chen , Li-Hsien Huang
IPC分类号： H01L23/544 , H01L21/66 , H01L21/768 , H01L23/48 , H01L25/18 , H01L21/56 , H01L23/528 , H01L25/065
CPC分类号： H01L23/544 , H01L21/56 , H01L21/561 , H01L21/6835 , H01L21/768 , H01L22/30 , H01L22/32 , H01L23/3128 , H01L23/481 , H01L23/528 , H01L24/10 , H01L24/18 , H01L25/0655 , H01L25/18 , H01L2221/68372 , H01L2221/68381 , H01L2223/54426 , H01L2223/5446 , H01L2223/54486
摘要： Test key structures, integrated circuit packages and methods of forming the same are disclosed. One of the test key structures includes a first pattern over a polymer layer, and at least one second pattern covering the first pattern. Besides, the second pattern and the first pattern have substantially the same outer profile, one of the first pattern and the second pattern includes a dielectric material and the other of the first pattern and the second pattern includes a metal material.
-
公开(公告)号：US20160351494A1
公开(公告)日：2016-12-01
申请号：US14724817
申请日：2015-05-29
发明人： Hsien-Wei Chen , An-Jhih Su , Li-Hsien Huang
IPC分类号： H01L23/522 , H01L21/3213 , H01L21/311 , H01L23/31
CPC分类号： H01L23/5226 , H01L21/311 , H01L21/568 , H01L23/3128 , H01L24/19 , H01L24/20 , H01L25/0657 , H01L25/105 , H01L25/50 , H01L2224/04105 , H01L2224/12105 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/73267 , H01L2224/92244 , H01L2225/0651 , H01L2225/06568 , H01L2225/1035 , H01L2225/1041 , H01L2225/1058 , H01L2924/15311 , H01L2924/181 , H01L2924/00012 , H01L2924/00014 , H01L2924/00
摘要： Device, package structure and method of forming the same are disclosed. The device includes a die encapsulated by an encapsulant, a conductive structure aside the die, and a dielectric layer overlying the conductive structure. The conductive structure includes a through via in the encapsulant, a redistribution line layer overlying the through via, and a seed layer overlying the redistribution line layer. The dielectric layer includes an opening, wherein the opening exposes a surface of the conductive structure, the opening has a scallop sidewall, and an included angle between a bottom surface of the dielectric layer and a sidewall of the opening is larger than about 60 degrees.
摘要翻译： 公开了装置，封装结构及其形成方法。 该器件包括由密封剂封装的管芯，除裸片之外的导电结构以及覆盖导电结构的介电层。 导电结构包括密封剂中的通孔，覆盖通孔的再分布线层和覆盖再分布线层的种子层。 电介质层包括开口，其中开口暴露导电结构的表面，开口具有扇形侧壁，并且电介质层的底表面和开口的侧壁之间的夹角大于约60度。
-
公开(公告)号：US12119320B2
公开(公告)日：2024-10-15
申请号：US17869118
申请日：2022-07-20
发明人： Wei-Yu Chen , Li-Hsien Huang , An-Jhih Su , Hsien-Wei Chen
IPC分类号： H01L23/00 , H01L21/48 , H01L21/54 , H01L21/56 , H01L23/31 , H01L23/498 , H01L25/00 , H01L25/065
CPC分类号： H01L24/16 , H01L21/486 , H01L21/54 , H01L21/565 , H01L23/3114 , H01L23/49827 , H01L24/01 , H01L24/11 , H01L24/18 , H01L25/0657 , H01L25/50 , H01L2224/02372 , H01L2224/11849 , H01L2224/16013 , H01L2224/16104 , H01L2224/16221 , H01L2225/06517 , H01L2225/06541
摘要： A chip package structure is provided. The chip package structure includes a redistribution structure and a first chip structure over the redistribution structure. The chip package structure also includes a first solder bump between the redistribution structure and the first chip structure and a first molding layer surrounding the first chip structure. The chip package structure further includes a second chip structure over the first chip structure and a second molding layer surrounding the second chip structure. In addition, the chip package structure includes a third molding layer surrounding the first molding layer, the second molding layer, and the first solder bump. A portion of the third molding layer is between the first molding layer and the redistribution structure.
-
公开(公告)号：US20240290823A1
公开(公告)日：2024-08-29
申请号：US18654658
申请日：2024-05-03
发明人： Hsien-Wei Chen , Ying-Ju Chen , Jie Chen , Ming-Fa Chen
IPC分类号： H01G4/30 , H01L21/768 , H01L23/522
CPC分类号： H01L28/60 , H01G4/30 , H01L21/76802 , H01L21/76877 , H01L23/5223 , H01L23/5226
摘要： Methods of forming a super high density metal-insulator-metal (SHDMIM) capacitor and semiconductor device are disclosed herein. A method includes depositing a first insulating layer over a semiconductor substrate and a series of conductive layers separated by a series of dielectric layers over the first insulating layer, the series of conductive layers including device electrodes and dummy metal plates. A first set of contact plugs through the series of conductive layers contacts one or more conductive layers of a first portion of the series of conductive layers. A second set of contact plugs through the series of dielectric layers avoids contact of a second portion of the series of conductive layers, the second portion of the series of conductive layers electrically floating.
-
公开(公告)号：US20240266297A1
公开(公告)日：2024-08-08
申请号：US18602718
申请日：2024-03-12
发明人： Ming-Fa Chen , Sung-Feng Yeh , Hsien-Wei Chen
IPC分类号： H01L23/538 , H01L21/48 , H01L21/56 , H01L21/683 , H01L21/78 , H01L23/00 , H01L23/31 , H01L25/00 , H01L25/10
CPC分类号： H01L23/5389 , H01L21/4853 , H01L21/4857 , H01L21/565 , H01L21/568 , H01L21/6835 , H01L21/78 , H01L23/3128 , H01L23/5383 , H01L23/5386 , H01L24/08 , H01L24/80 , H01L25/105 , H01L25/50 , H01L2221/68372 , H01L2224/08145 , H01L2224/80895 , H01L2224/80896 , H01L2225/1035 , H01L2225/1058
摘要： A package includes a redistribution structure, a die package on a first side of the redistribution structure including a first die connected to a second die by metal-to-metal bonding and dielectric-to-dielectric bonding, a dielectric material over the first die and the second die and surrounding the first die, and a first through via extending through the dielectric material and connected to the first die and a first via of the redistribution structure, a semiconductor device on the first side of the redistribution structure includes a conductive connector, wherein a second via of the redistribution structure contacts the conductive connector of the semiconductor device, a first molding material on the redistribution structure and surrounding the die package and the semiconductor device, and a package through via extending through the first molding material to contact a third via of the redistribution structure.
-
公开(公告)号：US20240153899A1
公开(公告)日：2024-05-09
申请号：US18411674
申请日：2024-01-12
发明人： Hsien-Wei Chen , Ming-Fa Chen , Chih-Chia Hu
IPC分类号： H01L23/00 , H01L23/495 , H01L23/498 , H03K19/1776
CPC分类号： H01L24/06 , H01L23/49503 , H01L23/49827 , H03K19/1776
摘要： A method includes polishing a semiconductor substrate of a first die to reveal first through-vias that extend into the semiconductor substrate, forming a dielectric layer on the semiconductor substrate, and forming a plurality of bond pads in the dielectric layer. The plurality of bond pads include active bond pads and dummy bond pads. The active bond pads are electrically coupled to the first through-vias. The first die is bonded to a second die, and both of the active bond pads and the dummy bond pads are bonded to corresponding bond pads in the second die.
-
公开(公告)号：US11908836B2
公开(公告)日：2024-02-20
申请号：US17314713
申请日：2021-05-07
发明人： Hsien-Wei Chen , Ming-Fa Chen
IPC分类号： H01L21/68 , H01L25/065 , H01L23/00 , H01L23/48 , H01L23/31 , H01L23/538 , H01L23/544 , H01L21/768 , H01L21/683 , H01L21/48 , H01L21/56 , H01L25/00 , H01L25/10
CPC分类号： H01L25/0657 , H01L21/4857 , H01L21/565 , H01L21/568 , H01L21/6835 , H01L21/76898 , H01L23/3128 , H01L23/481 , H01L23/5383 , H01L23/5386 , H01L23/5389 , H01L23/544 , H01L24/08 , H01L24/80 , H01L25/105 , H01L25/50 , H01L2221/68372 , H01L2223/54426 , H01L2224/08145 , H01L2224/80895 , H01L2224/80896 , H01L2225/0651 , H01L2225/06541 , H01L2225/06568 , H01L2225/06586 , H01L2225/06593 , H01L2225/1035 , H01L2225/1058 , H01L2225/1082
摘要： A semiconductor package includes a first die, a second die, an encapsulating material, and a redistribution structure. The second die is disposed over the first die and includes a plurality of bonding pads bonded to the first die, a plurality of through vias extending through a substrate of the second die and a plurality of alignment marks, wherein a pitch between adjacent two of the plurality of alignment marks is different from a pitch between adjacent two of the plurality of through vias. The encapsulating material is disposed over the first die and at least laterally encapsulating the second die. The redistribution structure is disposed over the second die and the encapsulating material and electrically connected to the plurality of through vias.
-
公开(公告)号：US20240021597A1
公开(公告)日：2024-01-18
申请号：US18366139
申请日：2023-08-07
发明人： Jie Chen , Hsien-Wei Chen , Ming-Fa Chen
IPC分类号： H01L25/18 , H01L23/31 , H01L23/498 , H01L23/48 , H01L23/538 , H01L23/00 , H01L25/00
CPC分类号： H01L25/18 , H01L23/3128 , H01L23/49816 , H01L23/481 , H01L23/5385 , H01L24/08 , H01L24/80 , H01L25/50 , H01L2224/80895 , H01L2224/08225 , H01L2224/80896
摘要： A package includes an interposer having a first redistribution structure; a first die directly bonded to a first surface of the first redistribution structure with a dielectric-to-dielectric bond and a metal-to-metal bond; a second die directly bonded to the first surface of the first redistribution structure with a dielectric-to-dielectric bond and a metal-to-metal bond; an encapsulant around the first die and the second die; and a plurality of conductive connectors on a second side of the first redistribution structure opposite to the first die and the second die.
-
公开(公告)号：US20240021554A1
公开(公告)日：2024-01-18
申请号：US18356538
申请日：2023-07-21
发明人： Hsien-Wei Chen , Ming-Fa Chen , Ying-Ju Chen
IPC分类号： H01L23/00 , H01L25/065 , H01L25/18 , H01L21/56 , H01L25/00
CPC分类号： H01L24/08 , H01L25/0657 , H01L25/18 , H01L21/565 , H01L24/80 , H01L25/50 , H01L25/0652 , H01L2924/1434 , H01L2225/06541 , H01L2225/06589 , H01L2225/06586 , H01L2224/08145 , H01L2224/80895 , H01L2224/80896 , H01L2924/1431
摘要： A semiconductor package includes a redistribution structure, a first device and a second device attached to the redistribution structure, the first device including: a first die, a support substrate bonded to a first surface of the first die, and a second die bonded to a second surface of the first die opposite the first surface, where a total height of the first die and the second die is less than a first height of the second device, and where a top surface of the substrate is at least as high as a top surface of the second device, and an encapsulant over the redistribution structure and surrounding the first device and the second device.
-
-
-
-
-
-
-
-
-
搜索结果
389 条记录 (耗时 0.031 秒)
