公开(公告)号：US20150364575A1

公开(公告)日：2015-12-17

申请号：US14835958

申请日：2015-08-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Bao-Ru Young ,  Wei Cheng Wu ,  Kong-Pin Chang ,  Chia Ming Liang ,  Meng-Fang Hsu ,  Ching-Feng Fu ,  Shih-Ting Hung

IPC: H01L29/66 ,  H01L21/762 ,  H01L21/8234

CPC classification number: H01L29/0649 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/66651 ,  H01L29/7833 ,  H01L29/7851

Abstract: Some embodiments of the present disclosure relate to a method. In this method, a semiconductor substrate, which has an active region disposed in the semiconductor substrate, is received. A shallow trench isolation (STI) structure is formed to laterally surround the active region. An upper surface of the active region bounded by the STI structure is recessed to below an upper surface of the STI structure. The recessed upper surface extends continuously between inner sidewalls of the STI structure and leaves upper portions of the inner sidewalls of the STI structure exposed. A semiconductor layer is epitaxially grown on the recessed surface of the active region between the inner sidewalls of the STI structure. A gate dielectric is formed over the epitaxially-grown semiconductor layer. A conductive gate electrode is formed over the gate dielectric.

Abstract translation: 本公开的一些实施例涉及一种方法。 在该方法中，接收具有设置在半导体衬底中的有源区的半导体衬底。 形成浅沟槽隔离（STI）结构以横向围绕有源区域。 由STI结构限定的有源区的上表面凹入到STI结构的上表面的下方。 凹陷的上表面在STI结构的内侧壁之间连续延伸，并且使STI结构的内侧壁的上部露出。 在STI结构的内侧壁之间的有源区的凹面上外延生长半导体层。 在外延生长的半导体层上形成栅极电介质。 在栅极电介质上形成导电栅电极。

公开(公告)号：US20150236030A1

公开(公告)日：2015-08-20

申请号：US14182952

申请日：2014-02-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Ming Wu ,  Wei Cheng Wu ,  Shih-Chang Liu ,  Harry-Hak-Lay Chuang ,  Chia-Shiung Tsai

IPC: H01L27/115 ,  H01L29/66 ,  H01L21/28 ,  H01L29/788

CPC classification number: H01L29/42344 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11521 ,  H01L27/11568 ,  H01L27/1157 ,  H01L29/42324 ,  H01L29/42348 ,  H01L29/518 ,  H01L29/6653 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/792

Abstract: The present disclosure relates to a split gate memory device which requires less number of processing steps than traditional baseline processes and methods of making the same. Word gate/select gate (SG) pairs are formed around a sacrificial spacer. The resulting SG structure has a distinguishable non-planar top surface. The spacer layer that covers the select gate also follows the shape of the SG top surface. A dielectric disposed above the inter-gate dielectric layer and arranged between the neighboring sidewalls of the each memory gate and select gate provides isolation between them.

Abstract translation: 本公开涉及一种分裂门存储器件，其需要比传统的基线工艺更少数量的处理步骤及其制造方法。 字栅/选择栅极（SG）对围绕牺牲间隔物形成。 所得到的SG结构具有可区分的非平面顶表面。 覆盖选择栅的间隔层也遵循SG顶表面的形状。 设置在栅极间介电层上方并且布置在每个存储器栅极和选择栅极的相邻侧壁之间的电介质在它们之间提供隔离。

公开(公告)号：US11688784B2

公开(公告)日：2023-06-27

申请号：US17218307

申请日：2021-03-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Te-Hsin Chiu ,  Wei Cheng Wu

IPC: H01L29/00 ,  H01L29/423 ,  H01L29/10 ,  H01L29/78 ,  H01L29/08 ,  H01L29/66 ,  H01L21/762 ,  H01L29/06 ,  H01L21/28

CPC classification number: H01L29/42376 ,  H01L21/28123 ,  H01L21/76224 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/4238 ,  H01L29/6659 ,  H01L29/66598 ,  H01L29/7833 ,  H01L29/7834 ,  H01L29/665

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes an isolation structure arranged within a substrate. The isolation structure has one or more surfaces defining one or more trenches that are recessed below an uppermost surface of the isolation structure and that are disposed along opposing sides of an active region of the substrate. A conductive gate is arranged over the substrate between a source region and a drain region. The conductive gate extends into the one or more trenches disposed along opposing sides of the active region of the substrate. The conductive gate has an upper surface that continuously extends past opposing sides of the one or more trenches.

公开(公告)号：US11488971B2

公开(公告)日：2022-11-01

申请号：US17104686

申请日：2020-11-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Te-Hsin Chiu ,  Wei Cheng Wu

IPC: H01L27/11536 ,  H01L21/027 ,  H01L21/28 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/762 ,  H01L21/768 ,  H01L27/11521 ,  H01L29/08 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/788 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11531 ,  H01L27/1157 ,  H01L27/11573 ,  H01L21/8234

Abstract: Various embodiments of the present application are directed to an IC, and associated forming methods. In some embodiments, the IC comprises a memory region and a logic region integrated in a substrate. A memory cell structure is disposed on the memory region. A logic device is disposed on the logic region having a logic gate electrode separated from the substrate by a logic gate dielectric. A sidewall spacer is disposed along a sidewall surface of the logic gate electrode. A contact etch stop layer (CESL) is disposed along an upper surface of the substrate, extending upwardly along and in direct contact with sidewall surfaces of the pair of select gate electrodes within the memory region, and extending upwardly along the sidewall spacer within the logic region.

公开(公告)号：US20220285382A1

公开(公告)日：2022-09-08

申请号：US17826503

申请日：2022-05-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Ming Wu ,  Wei Cheng Wu ,  Shih-Chang Liu ,  Harry-Hak-Lay Chuang ,  Chia-Shiung Tsai

IPC: H01L27/11568 ,  H01L29/792 ,  H01L29/423 ,  H01L21/311 ,  H01L29/66

Abstract: A device comprises a control gate structure and a memory gate structure over a substrate, a charge storage layer formed between the control gate structure and the memory gate structure, a first spacer along a sidewall of the memory gate structure, a second spacer along a sidewall of the control gate structure, an oxide layer over a top surface of the memory gate structure, a top spacer over the oxide layer, a first drain/source region formed in the substrate and adjacent to the memory gate structure and a second drain/source region formed in the substrate and adjacent to the control gate structure.

公开(公告)号：US11335786B2

公开(公告)日：2022-05-17

申请号：US16580296

申请日：2019-09-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei Cheng Wu ,  Alexander Kalnitsky ,  Shih-Hao Lo ,  Hung-Pin Ko

IPC: H01L29/49 ,  H01L29/423 ,  H01L29/66

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device including a gate structure. The semiconductor device further includes a pair of spacer segments on a semiconductor substrate. A high-κ gate dielectric structure overlies the semiconductor substrate. The high-κ gate dielectric structure is laterally between and borders the spacer segments. The gate structure overlies the high-k gate dielectric structure and has a top surface about even with a top surface of the spacer segments. The gate structure includes a metal structure and a gate body layer. The gate body layer has a top surface that is vertically offset from a top surface of the metal structure and further has a lower portion cupped by the metal structure.

公开(公告)号：US11282846B2

公开(公告)日：2022-03-22

申请号：US16430901

申请日：2019-06-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Feng Teng ,  Wei Cheng Wu

IPC: H01L27/115 ,  H01L27/11546 ,  H01L27/11529 ,  H01L27/11524 ,  H01L27/11534 ,  H01L29/788 ,  H01L29/423

Abstract: Various embodiments of the present application are directed to a method for forming an integrated circuit (IC), and the associated integrated circuit. In some embodiments, a substrate is provided including a logic region having a plurality of logic sub-regions including a low-voltage logic sub-region and a high-voltage logic sub-region. The method further comprises forming a stack of gate dielectric precursor layers on the plurality of logic sub-regions and removing the stack of gate dielectric precursor layers from the low-voltage logic sub-region and the high-voltage logic sub-region. The method further comprises forming a high-voltage gate dielectric precursor layer on the low-voltage logic sub-region and the high-voltage logic sub-region and removing the high-voltage gate dielectric precursor layer from the low-voltage logic sub-region. The low-voltage logic sub-region has a logic device configured to operate at a voltage smaller than that of another logic device of the high-voltage logic sub-region.

公开(公告)号：US20210288048A1

公开(公告)日：2021-09-16

申请号：US16858801

申请日：2020-04-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Wei Cheng Wu ,  Li-Feng Teng ,  Li-Jung Liu

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/417

Abstract: Various embodiments of the present disclosure are directed towards a method to embed planar field-effect transistor (FETs) with fin field-effect transistors (finFETs). A semiconductor substrate is patterned to define a mesa and a fin. A trench isolation structure is formed overlying the semiconductor substrate and surrounding the mesa and the fin. A first gate dielectric layer is formed on the mesa, but not the fin. The trench isolation structure recessed around the fin, but not the mesa, after the forming the first gate dielectric layer. A second gate dielectric layer is deposited overlying the first gate dielectric layer at the mesa and further overlying the fin. A first gate electrode is formed overlying the first and second gate dielectric layers at the mesa and partially defining a planar FET. A second gate electrode is formed overlying the second gate dielectric layer at the fin and partially defining a finFET.

公开(公告)号：US11069693B2

公开(公告)日：2021-07-20

申请号：US16545713

申请日：2019-08-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Wei Cheng Wu

IPC: H01L29/423 ,  H01L21/28 ,  H01L27/105 ,  H01L29/66 ,  H01L27/11521 ,  H01L27/11548 ,  H01L27/11526

Abstract: A method is provided for the manufacture of an integrated semiconductor device that includes an embedded flash memory array formed in a recessed region of a semiconductor substrate, the method includes, prior to formation of floating and control gate stacks of the memory array, depositing a protective layer over layers of gate material, and depositing a self-leveling sacrificial layer over the protective layer to produce a substantially planar upper surface. The sacrificial layer is then etched to a depth that removes the sacrificial layer and leaves a substantially planar face on the protective layer. A photo mask is then deposited on the protective layer and the gate stacks are etched from the layers of gate material.

公开(公告)号：US20210183880A1

公开(公告)日：2021-06-17

申请号：US17184953

申请日：2021-02-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Wei Cheng Wu ,  Ya-Chen Kao ,  Yi Hsien Lu

IPC: H01L27/11573 ,  H01L29/66 ,  H01L29/423 ,  H01L29/51 ,  H01L21/8234 ,  H01L27/092

Abstract: The present disclosure relates to an integrated circuit that includes a semiconductor substrate having a periphery region and memory cell region separated by a boundary region. A pair of split gate flash memory cells are disposed on the memory cell region and include a first select gate and a first memory gate. A first gate electrode is disposed over a first gate dielectric layer on the periphery region. A second gate electrode is disposed over a second gate dielectric layer on the periphery region at a position between the boundary region and the first gate electrode. The second dielectric layer is thicker than the first gate dielectric layer. The first select gate and the first memory gate have upper surfaces that are co-planar or level with the upper surface of the second gate electrode.