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公开(公告)号：US20190295955A1
公开(公告)日：2019-09-26
申请号：US16436494
申请日：2019-06-10
发明人： Cheng-Hsien Hsieh , Li-Han Hsu , Wei-Cheng Wu , Hsien-Wei Chen , Der-Chyang Yeh , Chi-Hsi Wu , Chen-Hua Yu
摘要： An embodiment device includes an integrated circuit die and a first metallization pattern over the integrated circuit die. The first metallization pattern includes a first dummy pattern having a first hole extending through a first conductive region. The device further includes a second metallization pattern over the first metallization pattern. The second metallization pattern includes a second dummy pattern having a second hole extending through a second conductive region. The second hole is arranged projectively overlapping a portion of the first hole and a portion of the first conductive region.
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公开(公告)号：US20190252334A1
公开(公告)日：2019-08-15
申请号：US16390814
申请日：2019-04-22
发明人： Cheng-Hsien Hsieh , Hsien-Wei Chen , Chen-Hua Yu , Tsung-Shu Lin , Wei-Cheng Wu
CPC分类号： H01L24/05 , H01L21/56 , H01L21/561 , H01L21/568 , H01L23/3128 , H01L23/481 , H01L23/562 , H01L24/03 , H01L24/11 , H01L24/13 , H01L24/19 , H01L25/105 , H01L25/50 , H01L2224/0231 , H01L2224/04105 , H01L2224/12105 , H01L2224/32145 , H01L2224/32225 , H01L2224/48227 , H01L2224/73265 , H01L2224/73267 , H01L2224/92244 , H01L2225/0651 , H01L2225/06568 , H01L2225/1023 , H01L2225/1041 , H01L2225/1058 , H01L2924/15311 , H01L2924/35121 , H01L2924/00012 , H01L2924/00
摘要： A redistribution layer with a landing pad is formed over a substrate with one or more mesh holes extending through the landing pad. The mesh holes may be arranged in a circular shape, and a passivation layer may be formed over the landing pad and the mesh holes. An opening is formed through the passivation layer and an underbump metallization is formed in contact with an exposed portion of the landing pad and extends over the mesh holes. By utilizing the mesh holes, sidewall delamination and peeling that might otherwise occur may be reduced or eliminated.
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公开(公告)号：US10373964B2
公开(公告)日：2019-08-06
申请号：US15864873
申请日：2018-01-08
IPC分类号： G11C11/00 , H01L27/11 , G11C11/412 , G11C11/419 , H01L23/522 , H01L23/528 , H01L23/532 , H01L49/02 , G11C5/02 , G11C5/14
摘要： A method, of writing to a memory cell, includes: causing a pulling device of the memory cell to pull a voltage level at a first data node of the memory cell toward a first supply voltage level responsive to a voltage level at a second data node of the memory cell; causing a pass gate of the memory cell to pull the voltage level at the first data node of the memory cell toward a second supply voltage level responsive to a word line signal, the second supply voltage level being different from the first supply voltage level; and limiting a driving capability of the pulling device by a resistive device, the resistive device being electrically coupled between the pulling device and a supply voltage source configured to provide a first supply voltage, the first supply voltage having the first supply voltage level.
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公开(公告)号：US10354961B2
公开(公告)日：2019-07-16
申请号：US15978621
申请日：2018-05-14
发明人： Chen-Hua Yu , Hsien-Wei Chen , Meng-Tsan Lee , Tsung-Shu Lin , Wei-Cheng Wu , Chien-Chia Chiu , Chin-Te Wang
IPC分类号： H01L23/00 , H01L23/538 , H01L23/31 , H01L21/48 , H01L21/56 , H01L25/10 , H01L25/00 , H01L23/498 , H01L21/683
摘要： A package includes a first dielectric layer, a device die over and attached to the first dielectric layer, an active through-via and a dummy through-via, and an encapsulating material encapsulating the device die, the active through-via, and the dummy through-via. The package further includes a second dielectric layer over and contacting the device die, the active through-via, and the dummy through-via. An active metal cap is over and contacting the second dielectric layer and electrically coupling to the active through-via. The active metal cap overlaps the active through-via. A dummy metal cap is over and contacting the second dielectric layer. The dummy metal cap overlaps the dummy through-via. The dummy metal cap is separated into a first portion and a second portion by a gap. A redistribution line passes through the gap between the first portion and the second portion of the dummy metal cap.
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公开(公告)号：US20190115300A1
公开(公告)日：2019-04-18
申请号：US16222219
申请日：2018-12-17
发明人： Chen-Hua Yu , An-Jhih Su , Chi-Hsi Wu , Der-Chyang Yeh , Ming Shih Yeh , Wei-Cheng Wu
IPC分类号： H01L23/538 , H01L21/56 , H01L25/16 , H01L21/768 , H01L21/3105 , H01L23/00 , H01L21/683 , H01L25/065 , H01L25/00
摘要： A multi-stacked package-on-package structure includes a method. The method includes: adhering a first die and a plurality of second dies to a substrate, the first die having a different function from each of the plurality of second dies; attaching a passive device over the first die; encapsulating the first die, the plurality of second dies, and the passive device; and forming a first redistribution structure over the passive device, the first die, and the plurality of second dies, the passive device connecting the first die to the first redistribution structure.
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公开(公告)号：US20190098756A1
公开(公告)日：2019-03-28
申请号：US16203919
申请日：2018-11-29
发明人： Cheng-Hsien Hsieh , Chi-Hsi Wu , Chen-Hua Yu , Der-Chyang Yeh , Hsien-Wei Chen , Li-Han Hsu , Wei-Cheng Wu
摘要： A package includes a conductive pad, with a plurality of openings penetrating through the conductive pad. A dielectric layer encircles the conductive pad. The dielectric layer has portions filling the plurality of openings. An Under-Bump Metallurgy (UBM) includes a via portion extending into the dielectric layer to contact the conductive pad. A solder region is overlying and contacting the UBM. An integrated passive device is bonded to the UBM through the solder region.
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公开(公告)号：US10165682B2
公开(公告)日：2018-12-25
申请号：US14979954
申请日：2015-12-28
发明人： Cheng-Hsien Hsieh , Chi-Hsi Wu , Chen-Hua Yu , Der-Chyang Yeh , Hsien-Wei Chen , Li-Han Hsu , Wei-Cheng Wu
摘要： A package includes a conductive pad, with a plurality of openings penetrating through the conductive pad. A dielectric layer encircles the conductive pad. The dielectric layer has portions filling the plurality of openings. An Under-Bump Metallurgy (UBM) includes a via portion extending into the dielectric layer to contact the conductive pad. A solder region is overlying and contacting the UBM. An integrated passive device is bonded to the UBM through the solder region.
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公开(公告)号：US20180323150A1
公开(公告)日：2018-11-08
申请号：US16023705
申请日：2018-06-29
发明人： Chen-Hua Yu , An-Jhih Su , Chi-Hsi Wu , Der-Chyang Yeh , Ming Shih Yeh , Wei-Cheng Wu
IPC分类号： H01L23/538 , H01L21/56 , H01L25/065 , H01L23/00 , H01L25/00 , H01L21/3105 , H01L21/768 , H01L25/16 , H01L21/683
CPC分类号： H01L23/5389 , H01L21/31053 , H01L21/565 , H01L21/568 , H01L21/6835 , H01L21/76802 , H01L24/19 , H01L24/24 , H01L25/0655 , H01L25/16 , H01L25/50 , H01L2221/68359 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/16145 , H01L2224/16227 , H01L2224/24137 , H01L2224/24195 , H01L2224/32145 , H01L2224/32225 , H01L2224/73204 , H01L2224/73259 , H01L2224/81005 , H01L2224/83005 , H01L2224/92125 , H01L2224/92224 , H01L2924/15311 , H01L2924/18161 , H01L2924/18162 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19102 , H01L2924/19104 , H01L2924/00
摘要： A multi-stacked package-on-package structure includes a method. The method includes: adhering a first die and a plurality of second dies to a substrate, the first die having a different function from each of the plurality of second dies; attaching a passive device over the first die; encapsulating the first die, the plurality of second dies, and the passive device; and forming a first redistribution structure over the passive device, the first die, and the plurality of second dies, the passive device connecting the first die to the first redistribution structure.
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公开(公告)号：US20180277520A1
公开(公告)日：2018-09-27
申请号：US15990055
申请日：2018-05-25
发明人： Chen-Hua Yu , An-Jhih Su , Wei-Yu Chen , Ying-Ju Chen , Tsung-Shu Lin , Chin-Chuan Chang , Hsien-Wei Chen , Wei-Cheng Wu , Li-Hsien Huang , Chi-Hsi Wu , Der-Chyang Yeh
IPC分类号： H01L25/065 , H01L25/00 , H01L21/48 , H01L21/56 , H01L21/78 , H01L23/31 , H01L23/498
CPC分类号： H01L25/0657 , H01L21/4853 , H01L21/486 , H01L21/56 , H01L21/78 , H01L23/3114 , H01L23/49811 , H01L23/49827 , H01L23/49838 , H01L25/0652 , H01L25/50 , H01L2224/04105 , H01L2224/12105 , H01L2224/18 , H01L2224/32225 , H01L2224/32245 , H01L2224/73267 , H01L2224/97 , H01L2225/06527 , H01L2225/06548 , H01L2225/06555 , H01L2924/3511 , H01L2224/83
摘要： A method includes attaching a first-level device die to a dummy die, encapsulating the first-level device die in a first encapsulating material, forming through-vias over and electrically coupled to the first-level device die, attaching a second-level device die over the first-level device die, and encapsulating the through-vias and the second-level device die in a second encapsulating material. Redistribution lines are formed over and electrically coupled to the through-vias and the second-level device die. The dummy die, the first-level device die, the first encapsulating material, the second-level device die, and the second encapsulating material form parts of a composite wafer.
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公开(公告)号：US20180277495A1
公开(公告)日：2018-09-27
申请号：US15989906
申请日：2018-05-25
发明人： Sao-Ling Chiu , Kuo-Ching Hsu , Wei-Cheng Wu , Ping-Kang Huang , Shang-Yun Hou , Shin-Puu Jeng , Chen-Hua Yu
CPC分类号： H01L23/562 , H01L21/4853 , H01L21/4857 , H01L21/486 , H01L21/561 , H01L21/563 , H01L21/565 , H01L21/76898 , H01L21/78 , H01L23/147 , H01L23/3128 , H01L23/3135 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L23/5384 , H01L24/16 , H01L24/97 , H01L25/0655 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/97 , H01L2924/15311 , H01L2924/181 , H01L2924/18161 , H01L2924/3511 , H01L2224/81 , H01L2224/83 , H01L2924/00
摘要： A package structure includes an interposer, a die over and bonded to the interposer, and a Printed Circuit Board (PCB) underlying and bonded to the interposer. The interposer is free from transistors therein (add transistor), and includes a semiconductor substrate, an interconnect structure over the semiconductor substrate, through-vias in the silicon substrate, and redistribution lines on a backside of the silicon substrate. The interconnect structure and the redistribution lines are electrically coupled through the through-vias.
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