公开(公告)号：US08344375B2

公开(公告)日：2013-01-01

申请号：US13312061

申请日：2011-12-06

Applicant: Nitin Kumar ,  Tony Chiang ,  Chi-I Lang ,  Prashant B Phatak ,  Jinhong Tong

Inventor： Nitin Kumar ,  Tony Chiang ,  Chi-I Lang ,  Prashant B Phatak ,  Jinhong Tong

IPC: H01L29/12 ,  H01L29/02

CPC classification number: G11C13/0007 ,  G11C2213/32 ,  G11C2213/52 ,  G11C2213/72 ,  G11C2213/73 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1608

Abstract: Nonvolatile memory elements are provided that have resistive switching metal oxides. The nonvolatile memory elements may be formed by depositing a metal-containing material on a silicon-containing material. The metal-containing material may be oxidized to form a resistive-switching metal oxide. The silicon in the silicon-containing material reacts with the metal in the metal-containing material when heat is applied. This forms a metal silicide lower electrode for the nonvolatile memory element. An upper electrode may be deposited on top of the metal oxide. Because the silicon in the silicon-containing layer reacts with some of the metal in the metal-containing layer, the resistive-switching metal oxide that is formed is metal deficient when compared to a stoichiometric metal oxide formed from the same metal.

Abstract translation: 提供具有电阻开关金属氧化物的非易失性存储元件。 非易失性存储元件可以通过将含金属的材料沉积在含硅材料上而形成。 含金属材料可以被氧化以形成电阻式开关金属氧化物。 当施加热量时，含硅材料中的硅与含金属材料中的金属反应。 这形成用于非易失性存储元件的金属硅化物下电极。 上部电极可以沉积在金属氧化物的顶部。 由于含硅层中的硅与含金属层中的一些金属反应，与由相同金属形成的化学计量的金属氧化物相比，形成的电阻 - 开关金属氧化物是金属缺陷的。

公开(公告)号：US20120325109A1

公开(公告)日：2012-12-27

申请号：US13335011

申请日：2011-12-22

Applicant: Bob Kong ,  Zhi-Wen Sun ,  Chi-I Lang ,  Jinhong Tong ,  Tony Chiang

Inventor： Bob Kong ,  Zhi-Wen Sun ,  Chi-I Lang ,  Jinhong Tong ,  Tony Chiang

IPC: C09D1/00

CPC classification number: H01L21/02068 ,  C23C18/1651 ,  C23C18/54 ,  H01L21/288 ,  H01L21/76852 ,  H01L21/76874

Abstract: Embodiments of the current invention describe methods of processing a semiconductor substrate that include applying a zincating solution to the semiconductor substrate to form a zinc passivation layer on the titanium-containing layer, the zincating solution comprising a zinc salt, FeCl3, and a pH adjuster.

Abstract translation: 本发明的实施方案描述了处理半导体衬底的方法，其包括将锌化溶液施加到半导体衬底上以在含钛层上形成锌钝化层，所述锌化溶液包含锌盐FeCl 3和pH调节剂。

公开(公告)号：US20120319070A1

公开(公告)日：2012-12-20

申请号：US13333742

申请日：2011-12-21

Applicant: Pragati Kumar ,  Sandra G. Malhotra ,  Sean Barstow ,  Tony Chiang

Inventor： Pragati Kumar ,  Sandra G. Malhotra ,  Sean Barstow ,  Tony Chiang

IPC: H01L47/00

CPC classification number: H01L45/1253 ,  G11C13/0007 ,  G11C13/003 ,  G11C2213/32 ,  G11C2213/51 ,  G11C2213/52 ,  G11C2213/56 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/74 ,  G11C2213/76 ,  G11C2213/79 ,  H01L27/2409 ,  H01L27/2463 ,  H01L29/861 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146 ,  H01L45/1608 ,  H01L45/165

Abstract: Nonvolatile memory elements are provided comprising switching metal oxides. The nonvolatile memory elements may be formed in one or more layers on an integrated circuit. Each memory element may have a first conductive layer, a metal oxide layer, and a second conductive layer. Electrical devices may be coupled in series with the memory elements. The first conductive layer may be formed from a metal nitride. The metal oxide layer may contain the same metal as the first conductive layer. The metal oxide may form an ohmic contact or a Schottky contact with the first conductive layer. The second conductive layer may form an ohmic contact or a Schottky contact with the metal oxide layer. The first conductive layer, the metal oxide layer, and the second conductive layer may include sublayers. The second conductive layer may include an adhesion or barrier layer and a workfunction control layer.

Abstract translation: 提供包括开关金属氧化物的非易失性存储元件。 非易失性存储元件可以形成在集成电路上的一个或多个层中。 每个存储元件可以具有第一导电层，金属氧化物层和第二导电层。 电气设备可以与存储器元件串联耦合。 第一导电层可以由金属氮化物形成。 金属氧化物层可以包含与第一导电层相同的金属。 金属氧化物可以与第一导电层形成欧姆接触或肖特基接触。 第二导电层可以与金属氧化物层形成欧姆接触或肖特基接触。 第一导电层，金属氧化物层和第二导电层可以包括子层。 第二导电层可以包括粘合或阻挡层和功函数控制层。

公开(公告)号：US20120258255A1

公开(公告)日：2012-10-11

申请号：US13081042

申请日：2011-04-06

Applicant: Hong Sheng Yang ,  Chi-I Lang ,  Tony Chiang

Inventor： Hong Sheng Yang ,  Chi-I Lang ,  Tony Chiang

IPC: C23C14/00

CPC classification number: C23C14/34 ,  C23C14/54 ,  C23C14/548 ,  H01J37/3447

Abstract: The present disclosure includes a method for control of a film composition with co-sputter physical vapor deposition. In one implementation, the method includes: positioning first and second PVD guns above a substrate, selecting first and second collimators having first and second sets of physical characteristics, positioning the first and second collimators between the first and second PVD guns and the substrate, sputtering at least one material from the first and second PVD guns through the first and second collimators upon application of a first power and second power, wherein the first PVD gun has a first deposition rate from the first collimator at the first power, and the second PVD gun has a second deposition rate from the second collimator at the second power.

Abstract translation: 本公开内容包括用于控制具有共溅射物理气相沉积的膜组合物的方法。 在一个实施方案中，该方法包括：将第一和第二PVD枪定位在衬底上方，选择具有第一和第二组物理特性的第一和第二准直器，将第一和第二准直器定位在第一和第二PVD枪和衬底之间，溅射 在施加第一功率和第二功率时，来自第一和第二PVD枪的至少一种材料通过第一和第二准直器，其中第一PVD枪具有来自第一准直器的第一沉积速率，而第二PVD 枪在第二功率下具有来自第二准直器的第二沉积速率。

公开(公告)号：US20120256155A1

公开(公告)日：2012-10-11

申请号：US13249631

申请日：2011-09-30

Applicant: Wayne French ,  Pragati Kumar ,  Prashant Phatak ,  Tony Chiang

Inventor： Wayne French ,  Pragati Kumar ,  Prashant Phatak ,  Tony Chiang

IPC: H01L45/00

CPC classification number: C23C14/083 ,  C23C14/0042 ,  C23C14/54 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/165

Abstract: This disclosure provides a method of fabricating a semiconductor device layer and an associated memory cell. Empirical data may be used to generate a hysteresis curve associated with deposition for a metal-insulator-metal structure, with curve measurements reflecting variance of an electrical property as a function of cathode voltage used during a sputtering process. By generating at least one voltage level to be used during the sputtering process, where the voltage reflects a suitable value for the electrical property from among the values obtainable in mixed-mode deposition, a semiconductor device layer may be produced with improved characteristics and durability. A multistable memory cell or array of such cells manufactured according to this process can, for a set of given materials, be fabricated to have minimal leakage or “off” current characteristics (Ileak or Ioff, respectively) or a maximum ratio of “on” current to “off” current (Ion/Ioff).

Abstract translation: 本公开提供了制造半导体器件层和相关联的存储单元的方法。 经验数据可用于产生与金属 - 绝缘体 - 金属结构的沉积相关联的滞后曲线，其中曲线测量反映作为在溅射过程中使用的阴极电压的函数的电特性的变化。 通过在溅射过程中产生要使用的至少一个电压电平，其中电压从混合模式沉积中可获得的值中反映适合的电特性值，可以制造具有改进的特性和耐久性的半导体器件层。 对于一组给定材料制造的这种电池的多电平存储器单元或阵列可以被制造成具有最小的泄漏或截止电流特性（分别为Ileak或Ioff）或电流与截止电流的最大比率 （Ion / Ioff）。

公开(公告)号：US20120205610A1

公开(公告)日：2012-08-16

申请号：US13454392

申请日：2012-04-24

Applicant: Prashant Phatak ,  Tony Chiang ,  Michael Miller ,  Wen Wu

Inventor： Prashant Phatak ,  Tony Chiang ,  Michael Miller ,  Wen Wu

IPC: H01L45/00

CPC classification number: H01L45/1616 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/10 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146

Abstract: A resistive switching memory element including a doped silicon electrode is described, including a first electrode comprising doped silicon having a first work function, a second electrode having a second work function that is different from the first work function by between 0.1 and 1.0 electron volts (eV), a metal oxide layer between the first electrode and the second electrode, the metal oxide layer switches using bulk-mediated switching and has a bandgap of greater than 4 eV, and the memory element switches from a low resistance state to a high resistance state and vice versa.

Abstract translation: 描述了包括掺杂硅电极的电阻式开关存储元件，其包括包括具有第一功函数的掺杂硅的第一电极，具有与第一功函数不同的第二功函数的第二电极在0.1和1.0电子伏特之间 eV），第一电极和第二电极之间的金属氧化物层，金属氧化物层使用体积介导的开关进行开关，并且具有大于4eV的带隙，并且存储元件从低电阻状态切换到高电阻 状态，反之亦然。

公开(公告)号：US20120094503A1

公开(公告)日：2012-04-19

申请号：US13334549

申请日：2011-12-22

Applicant: Sunil Shanker ,  Tony Chiang

Inventor： Sunil Shanker ,  Tony Chiang

IPC: H01L21/30

CPC classification number: C23C16/047 ,  C23C16/04 ,  C23C16/45536 ,  C23C16/45551 ,  C23C16/45565 ,  C23C16/45574 ,  C23C16/45591 ,  C23C16/4583 ,  C23C16/46 ,  C23C16/50 ,  C23C16/5096 ,  C23C16/52 ,  H01J37/32357 ,  H01J37/32366

Abstract: Combinatorial plasma enhanced deposition techniques are described, including designating multiple regions of a substrate, providing a precursor to at least a first region of the multiple regions, and providing a plasma to the first region to deposit a first material on the first region formed using the first precursor, wherein the first material is different from a second material formed on a second region of the substrate.

Abstract translation: 描述组合等离子体增强沉积技术，包括指定衬底的多个区域，为多个区域的至少第一区域提供前体，以及向第一区域提供等离子体，以将第一材料沉积在使用 第一前体，其中所述第一材料不同于形成在所述基底的第二区域上的第二材料。

公开(公告)号：US08158511B2

公开(公告)日：2012-04-17

申请号：US13068821

申请日：2011-05-20

Applicant: Tony Chiang ,  Gongda Yao ,  Peijun Ding ,  Fusen E. Chen ,  Barry L. Chin ,  Gene Y. Kohara ,  Zheng Xu ,  Hong Zhang

Inventor： Tony Chiang ,  Gongda Yao ,  Peijun Ding ,  Fusen E. Chen ,  Barry L. Chin ,  Gene Y. Kohara ,  Zheng Xu ,  Hong Zhang

IPC: H01L21/44

CPC classification number: H01L21/76843 ,  C23C14/046 ,  C23C14/165 ,  H01L21/2855 ,  H01L21/76805 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76862 ,  H01L21/76865 ,  H01L21/76871 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76883

Abstract: A method of depositing a metal seed layer with underlying barrier layer on a wafer substrate comprising a plurality of recessed device features. A first portion of the barrier layer is deposited on the wafer substrate without excessive build-up of barrier layer material on the openings to the plurality of recessed device features, while obtaining bottom coverage without substantial sputtering of the bottom surface. Subsequently, a metal seed layer is deposited using the same techniques used to deposit the barrier layer, to avoid excessive build up of metal seed layer material on the openings to the features, with minimal sputtering of the barrier layer surface.

Abstract translation: 一种在晶片衬底上沉积具有下层阻挡层的金属种子层的方法，包括多个凹陷的器件特征。 阻挡层的第一部分沉积在晶片衬底上，而不会在与多个凹陷器件特征的开口上过多地形成阻挡层材料，同时获得底部覆盖而无需基本上溅射底部表面。 随后，使用与沉积阻挡层相同的技术沉积金属种子层，以避免金属种子层材料在具有特征的开口上的过度积累，同时阻挡层表面的溅射最少。

公开(公告)号：US20120088328A1

公开(公告)日：2012-04-12

申请号：US13329253

申请日：2011-12-17

Applicant: Prashant Phatak ,  Tony Chiang ,  Pragati Kumar ,  Michael Miller

Inventor： Prashant Phatak ,  Tony Chiang ,  Pragati Kumar ,  Michael Miller

IPC: H01L21/8239

CPC classification number: H01L45/146 ,  G11C13/0007 ,  G11C2213/32 ,  G11C2213/55 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/2463 ,  H01L29/8615 ,  H01L45/08 ,  H01L45/10 ,  H01L45/122 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/1616 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/165 ,  H01L45/1658 ,  H01L47/00

Abstract: Non-volatile resistive-switching memories are described, including a memory element having a first electrode, a second electrode, a metal oxide between the first electrode and the second electrode. The metal oxide switches using bulk-mediated switching, has a bandgap greater than 4 electron volts (eV), has a set voltage for a set operation of at least one volt per one hundred angstroms of a thickness of the metal oxide, and has a leakage current density less than 40 amps per square centimeter (A/cm2) measured at 0.5 volts (V) per twenty angstroms of the thickness of the metal oxide.

Abstract translation: 描述了非易失性电阻式切换存储器，包括在第一电极和第二电极之间具有第一电极，第二电极，金属氧化物的存储元件。 使用大容量介导的开关的金属氧化物开关具有大于4电子伏特（eV）的带隙，具有用于金属氧化物的厚度每100埃至少一伏特的设定操作的设定电压，并且具有 漏电流密度小于每平方厘米40安培（A / cm2），每0.5伏（V），金属氧化物厚度每20埃测得。

公开(公告)号：US20120074376A1

公开(公告)日：2012-03-29

申请号：US13312061

申请日：2011-12-06

Applicant: Nitin Kumar ,  Jinhong Tong ,  Chi-I Lang ,  Tony Chiang ,  Prashant B. Phatak

Inventor： Nitin Kumar ,  Jinhong Tong ,  Chi-I Lang ,  Tony Chiang ,  Prashant B. Phatak

IPC: H01L47/00

CPC classification number: G11C13/0007 ,  G11C2213/32 ,  G11C2213/52 ,  G11C2213/72 ,  G11C2213/73 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1608

Abstract: Nonvolatile memory elements are provided that have resistive switching metal oxides. The nonvolatile memory elements may be formed by depositing a metal-containing material on a silicon-containing material. The metal-containing material may be oxidized to form a resistive-switching metal oxide. The silicon in the silicon-containing material reacts with the metal in the metal-containing material when heat is applied. This forms a metal silicide lower electrode for the nonvolatile memory element. An upper electrode may be deposited on top of the metal oxide. Because the silicon in the silicon-containing layer reacts with some of the metal in the metal-containing layer, the resistive-switching metal oxide that is formed is metal deficient when compared to a stoichiometric metal oxide formed from the same metal.

Abstract translation: 提供具有电阻开关金属氧化物的非易失性存储元件。 非易失性存储元件可以通过将含金属的材料沉积在含硅材料上而形成。 含金属材料可以被氧化以形成电阻式开关金属氧化物。 当施加热量时，含硅材料中的硅与含金属材料中的金属反应。 这形成用于非易失性存储元件的金属硅化物下电极。 上部电极可以沉积在金属氧化物的顶部。 由于含硅层中的硅与含金属层中的一些金属反应，与由相同金属形成的化学计量的金属氧化物相比，形成的电阻 - 开关金属氧化物是金属缺陷的。