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    Semiconductor memory device capable of reducing power consumption in self-refresh operation
    81.
    发明授权
    Semiconductor memory device capable of reducing power consumption in self-refresh operation 有权
    能够降低自刷新操作中的功耗的半导体存储器件

    公开(公告)号：US06349068B2

    公开(公告)日：2002-02-19

    申请号：US09828847

    申请日：2001-04-10

    申请人： Yoshihiro Takemae ,  Yasurou Matsuzaki

    发明人： Yoshihiro Takemae ,  Yasurou Matsuzaki

    IPC分类号： G11C700

    CPC分类号： G11C11/40622 ,  G11C11/406

    摘要： A semiconductor memory device, which refreshes memory cells to retain data, has a first refresh mode and a second refresh mode. The first refresh mode is a mode for refreshing all of the memory cells, and the second refresh mode is a mode for refreshing a part of the memory cells. By refreshing only designated areas where data must be retained, power consumption in a refresh operation can be reduced, drastically cutting power consumption in a power-down mode.

    摘要翻译： 刷新存储单元以保留数据的半导体存储器件具有第一刷新模式和第二刷新模式。 第一刷新模式是用于刷新所有存储单元的模式，第二刷新模式是用于刷新存储单元的一部分的模式。 通过仅刷新必须保留数据的指定区域，可以减少刷新操作中的功耗，从而在掉电模式下大幅度地削减功耗。

    Semiconductor integrated circuit with input/output interface adapted for small-amplitude operation
    86.
    发明授权
    Semiconductor integrated circuit with input/output interface adapted for small-amplitude operation 失效
    具有适用于小振幅操作的输入/输出接口的半导体集成电路

    公开(公告)号：US5557221A

    公开(公告)日：1996-09-17

    申请号：US76434

    申请日：1993-06-14

    申请人： Masao Taguchi ,  Satoshi Eto ,  Yoshihiro Takemae ,  Hiroshi Yoshioka ,  Makoto Koga

    发明人： Masao Taguchi ,  Satoshi Eto ,  Yoshihiro Takemae ,  Hiroshi Yoshioka ,  Makoto Koga

    IPC分类号： H03K19/0185 ,  H03F3/45

    CPC分类号： H03K19/018585

    摘要： A semiconductor integrated circuit includes a switch unit for controlling the supply of a power source voltage to a signal amplification circuit for receiving an input signal, and a control unit for selectively turning ON and OFF the switch unit in accordance with the amplitude or frequency of this input signal. By the constitution, it is possible to provide an input circuit or an output circuit capable of being applied to an input/output interface adapted for a small amplitude operation.

    摘要翻译： 半导体集成电路包括用于控制向接收输入信号的信号放大电路提供电源电压的开关单元，以及根据该开关单元的幅度或频率选择性地接通和断开开关单元的控制单元 输入信号。 通过该结构，可以提供能够应用于适于小振幅操作的输入/输出接口的输入电路或输出电路。

    Semiconductor memory device and method of forming the same
    87.
    发明授权
    Semiconductor memory device and method of forming the same 失效
    半导体存储器件及其形成方法

    公开(公告)号：US5537354A

    公开(公告)日：1996-07-16

    申请号：US357307

    申请日：1994-12-14

    申请人： Hirohiko Mochizuki ,  Yoshihiro Takemae ,  Yukinori Kodama ,  Makoto Yanagisawa ,  Hiroyoshi Tomita

    发明人： Hirohiko Mochizuki ,  Yoshihiro Takemae ,  Yukinori Kodama ,  Makoto Yanagisawa ,  Hiroyoshi Tomita

    IPC分类号： G11C11/401 ,  F02B75/02 ,  G11C7/10 ,  G11C11/407 ,  G11C11/409 ,  G11C13/00

    CPC分类号： G11C7/1072 ,  F02B2075/025

    摘要： A method of making an SDRAM (synchronous dynamic random access memory) into either a low-speed type or a high-speed type includes the steps of determining an electrical connection of a predetermined electrode of the SDRAM, and providing the predetermined electrode with a voltage level defined by the electrical connection, the voltage level determining whether the SDRAM is made into the low-speed type or the high speed type, wherein the low-speed type can carry out consecutive writing operations at a low clock rate for two addresses having the same row address, and the high-speed type can carry out simultaneous writing operations at a high clock rate for two addresses having the same row address and consecutive column addresses.

    摘要翻译： 将SDRAM（同步动态随机存取存储器）制成低速型或高速型的方法包括以下步骤：确定SDRAM的预定电极的电连接，并为预定电极提供电压 由电气连接限定的电平，电压电平确定SDRAM是低速型还是高速型，其中低速类型可以以低时钟速率对具有 相同的行地址，并且高速类型可以以具有相同行地址和连续列地址的两个地址以高时钟速率执行同时写入操作。

    Semiconductor memory unit having redundant structure
    88.
    发明授权
    Semiconductor memory unit having redundant structure 失效
    具有冗余结构的半导体存储单元

    公开(公告)号：US5307316A

    公开(公告)日：1994-04-26

    申请号：US861822

    申请日：1992-06-16

    申请人： Yoshihiro Takemae

    发明人： Yoshihiro Takemae

    IPC分类号： H01L27/10 ,  G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  H01L21/86 ,  G11C7/00

    CPC分类号： G11C29/81 ,  G11C29/832

    摘要： A semiconductor memory device has a plurality of main memory blocks formed on a chip and each having a redundancy, a sub-memory block formed on the chip and having a substantially identical construction as that of each main memory block, a defect address memory circuit for storing address data of the main memory block that cannot be saved by the redundancy, and a redundancy control circuit for selecting the sub-memory block when a defective main memory block is selected.

    摘要翻译： PCT No.PCT / JP91 / 01406 Sec。 371日期：1992年6月16日 102（e）日期1992年6月16日PCT 1991年10月16日PCT公布。 公开号WO92 / 07362 日期：1992年04月30日。半导体存储器件具有形成在芯片上并具有冗余的多个主存储器块，形成在芯片上的子存储块，并且具有与每个主存储器块相同的结构 ，用于存储不能由冗余保存的主存储块的地址数据的缺陷地址存储电路，以及当选择缺陷主存储块时用于选择子存储块的冗余控制电路。

    Static semiconductor memory with readout inhibit means
    89.
    发明授权
    Static semiconductor memory with readout inhibit means 失效
    具有读出禁止装置的静态半导体存储器

    公开(公告)号：US4982366A

    公开(公告)日：1991-01-01

    申请号：US467348

    申请日：1990-01-22

    申请人： Yoshihiro Takemae

    发明人： Yoshihiro Takemae

    IPC分类号： G11C11/413 ,  G06F11/16 ,  G11C8/20 ,  G11C11/409 ,  G11C11/418 ,  G11C29/00 ,  G11C29/04 ,  H01L27/10

    CPC分类号： G11C8/20 ,  G05B2219/25381

    摘要： A static semiconductor memory device includes a memory cell array including a large number of static memory cells arranged in a matrix fashion, a word decoder, a column decoder, and a data buffer. An address delay buffer is provided for delaying an input address signal by a predetermined delay time and a comparator circuit is provided for comparing the input address signal with the delayed address signal from the address delay buffer, so that even if the input address signal is disturbed by noise, the erroneous data corresponding to the disturbed address signal is not read into the data buffer by means of the output signal of the comparator circuit and is not output from the memory device.

    摘要翻译： 静态半导体存储器件包括存储单元阵列，其包括以矩阵方式布置的大量静态存储器单元，字解码器，列解码器和数据缓冲器。 提供地址延迟缓冲器用于将输入地址信号延迟预定的延迟时间，并且提供比较器电路用于将输入地址信号与来自地址延迟缓冲器的延迟地址信号进行比较，使得即使输入地址信号被干扰 通过噪声，与干扰的地址信号相对应的错误数据不通过比较器电路的输出信号被读入数据缓冲器，并且不从存储器件输出。

    Semiconductor memory device with internal array transfer capability
    90.
    发明授权
    Semiconductor memory device with internal array transfer capability 失效
    具有内部阵列传输能力的半导体存储器件

    公开(公告)号：US4879685A

    公开(公告)日：1989-11-07

    申请号：US311367

    申请日：1989-02-16

    申请人： Yoshihiro Takemae

    发明人： Yoshihiro Takemae

    IPC分类号： G11C7/00 ,  G11C8/04 ,  G11C11/401 ,  H01L27/10

    CPC分类号： G11C7/00 ,  G11C8/04

    摘要： A semiconductor memory device includes, a plurality of word lines, a plurality of bit lines and a plurality of memory cells each connected between the word lines and the bit lines at each intersection of the word lines and bit lines. A plurality of sense amplifiers, each connected to each pair of bit lines, are for amplifying a difference in potential between each of the bit lines; a plurality of bit line reset circuits, each connected to each pair of the bit lines, the difference in potential being held during the read/write cycles. A transfer mode setting circuit is for optionally selecting a first word line and thereafter selecting a second word line, and for simultaneously reading out data in each memory cell connected to the first word line onto each bit line and thereafter simultaneously writing data on each bit line amplified by the sense amplifier into each corresponding memory cell connected to the second word line.

    摘要翻译： 半导体存储器件包括多个字线，多个位线和多个存储单元，每个位线和字线连接在字线和位线之间的字线和位线的每个交叉处。 每个连接到每对位线的多个读出放大器用于放大每个位线之间的电位差; 多个位线复位电路，每个连接到每对位线，在读/写周期期间电位差被保持。 传输模式设置电路用于可选地选择第一字线，然后选择第二字线，并且用于同时将连接到第一字线的每个存储单元中的数据读出到每个位线上，然后同时在每个位线上写入数据 由读出放大器放大成连接到第二字线的每个对应的存储单元。