公开(公告)号：US20140087076A1

公开(公告)日：2014-03-27

申请号：US13950049

申请日：2013-07-24

Applicant: ASM International N.V.

Inventor： Suvi P. Haukka ,  Marko J. Tuominen ,  Antti Rahtu

IPC: C23C16/08 ,  C23C16/18

CPC classification number: C23C16/08 ,  C23C16/0218 ,  C23C16/18 ,  C23C16/45525 ,  H01L21/28562

Abstract: The invention relates generally to processes for enhancing the deposition of noble metal thin films on a substrate by atomic layer deposition. Treatment with gaseous halides or metalorganic compounds reduces the incubation time for deposition of noble metals on particular surfaces. The methods may be utilized to facilitate selective deposition. For example, selective deposition of noble metals on high-k materials relative to insulators can be enhanced by pretreatment with halide reactants. In addition, halide treatment can be used to avoid deposition on the quartz walls of the reaction chamber.

Abstract translation: 本发明一般涉及通过原子层沉积来增强在衬底上沉积贵金属薄膜的方法。 使用气态卤化物或金属有机化合物进行处理减少了在特定表面上沉积贵金属的孵育时间。 该方法可用于促进选择性沉积。 例如，可以通过用卤化物反应物预处理来提高贵金属在高k材料上相对于绝缘体的选择性沉积。 此外，可以使用卤化物处理以避免沉积在反应室的石英壁上。

公开(公告)号：US08658259B2

公开(公告)日：2014-02-25

申请号：US12732825

申请日：2010-03-26

Applicant: Tue Nguyen ,  Tai Dung Nguyen

Inventor： Tue Nguyen ,  Tai Dung Nguyen

IPC: C23C16/00 ,  H05H1/00

CPC classification number: C23C16/45525 ,  C23C16/56

Abstract: A hybrid deposition process of CVD and ALD, called NanoLayer Deposition (NLD) is provided. The nanolayer deposition process is a cyclic sequential deposition process, comprising the first step of introducing a first plurality of precursors to deposit a thin film with the deposition process not self-limiting, then a second step of purging the first set of precursors and a third step of introducing a second plurality of precursors to modify the deposited thin film. The deposition step in the NLD process using the first set of precursors is not self limiting and is a function of substrate temperature and process time. The second set of precursors modifies the already deposited film characteristics. The second set of precursors can treat the deposited film such as a modification of film composition, a doping or a removal of impurities from the deposited film. The second set of precursors can also deposit another layer on the deposited film. The additional layer can react with the existing layer to form a compound layer, or can have minimum reaction to form a nanolaminate film.

Abstract translation: 提供了称为NanoLayer沉积（NLD）的CVD和ALD的混合沉积工艺。 纳米层沉积工艺是循环顺序沉积工艺，包括引入第一多个前体以沉积薄膜而不是自限制的沉积工艺的第一步骤，然后第二步骤是清洗第一组前体和第三步 引入第二多个前体以修饰沉积的薄膜的步骤。 使用第一组前体的NLD工艺中的沉积步骤不是自限制的，并且是衬底温度和处理时间的函数。 第二组前体改变已沉积的膜特性。 第二组前体可以处理沉积的膜，例如膜组成的改变，掺杂或从沉积膜去除杂质。 第二组前体也可以在沉积膜上沉积另一层。 附加层可以与现有层反应以形成化合物层，或者可以具有最小的反应以形成纳米层间膜。

公开(公告)号：US08652573B2

公开(公告)日：2014-02-18

申请号：US13183016

申请日：2011-07-14

Applicant: Maarten Stokhof ,  Hessel Sprey ,  Tatsuya Yoshimi ,  Bert Jongbloed ,  Noureddine Adjeroud

Inventor： Maarten Stokhof ,  Hessel Sprey ,  Tatsuya Yoshimi ,  Bert Jongbloed ,  Noureddine Adjeroud

IPC: C23C16/00 ,  C23C16/08

CPC classification number: C23C16/34 ,  C23C16/45523

Abstract: Method of depositing a film having a substantially uniform thickness by means of chemical vapor deposition, comprising: providing a reaction chamber; providing a substrate in said reaction chamber; subjecting the substrate to a series of deposition cycles, wherein each deposition cycle includes the steps of: (a) during a first time interval, supplying a first reactant to the reaction chamber; (b) during a second time interval, supplying a second reactant to the reaction chamber; and (c) during a third time interval, supplying neither the first nor the second reactant to the reaction chamber; wherein a start of the second time interval lies within the first time interval, such that a pre-exposure interval exists between a start of the first time interval and the start of the second time interval, during which pre-exposure interval the first reactant is supplied to the reaction chamber while the second reactant is not.

Abstract translation: 通过化学气相沉积沉积具有基本均匀厚度的膜的方法，包括：提供反应室; 在所述反应室中提供衬底; 对衬底进行一系列沉积循环，其中每个沉积循环包括以下步骤：（a）在第一时间间隔期间，向反应室供应第一反应物; （b）在第二时间间隔期间，向所述反应室供应第二反应物; 和（c）在第三时间间隔期间，第一和第二反应物都不向反应室供应; 其中所述第二时间间隔的开始位于所述第一时间间隔内，使得在所述第一时间间隔的开始和所述第二时间间隔的开始之间存在预曝光间隔，在所述预曝光间隔期间，所述第一反应物为 供应到反应室，而第二反应物不是。

公开(公告)号：US08524322B2

公开(公告)日：2013-09-03

申请号：US12979449

申请日：2010-12-28

Applicant: Tom E Blomberg

Inventor： Tom E Blomberg

IPC: C23C16/00 ,  C23C16/08

CPC classification number: C23C16/44 ,  C23C16/45525 ,  C23C16/45544

Abstract: The present invention relates generally to methods and apparatus for the controlled growing of material on substrates. According to embodiments of the present invention, a precursor fed is split in to two paths from a precursor source. One of the paths is restricted in a continuous manner. The other path is restricted in a periodic manner. The output of the two paths converges at a point prior to entry of the reactor. Therefore, a single precursor source is able to fed precursor in to a reactor under two different conditions, one which can be seen as mimicking ALD conditions and one which can be seen as mimicking CVD conditions. This allows for an otherwise single mode reactor to be operated in a plurality of modes including one or more ALD/CVD combination modes.

Abstract translation: 本发明一般涉及在衬底上控制生长材料的方法和装置。 根据本发明的实施方案，将前体进料分离成来自前体源的两条路径。 其中一条路径以连续的方式受到限制。 另一条路径被定期地限制。 两个路径的输出在反应器进入之前的某一点收敛。 因此，单个前体源能够在两种不同的条件下将前体进料到反应器中，其可以被看作模拟ALD条件，也可以被看作模拟CVD条件。 这允许否则单模电抗器以包括一个或多个ALD / CVD组合模式的多种模式操作。

公开(公告)号：US08501275B2

公开(公告)日：2013-08-06

申请号：US13239090

申请日：2011-09-21

Applicant: Suvi P. Haukka ,  Marko J. Tuominen ,  Antti Rahtu

Inventor： Suvi P. Haukka ,  Marko J. Tuominen ,  Antti Rahtu

IPC: C23C16/00

CPC classification number: C23C16/08 ,  C23C16/0218 ,  C23C16/18 ,  C23C16/45525 ,  H01L21/28562

Abstract: The invention relates generally to processes for enhancing the deposition of noble metal thin films on a substrate by atomic layer deposition. Treatment with gaseous halides or metalorganic compounds reduces the incubation time for deposition of noble metals on particular surfaces. The methods may be utilized to facilitate selective deposition. For example, selective deposition of noble metals on high-k materials relative to insulators can be enhanced by pretreatment with halide reactants. In addition, halide treatment can be used to avoid deposition on the quartz walls of the reaction chamber.

Abstract translation: 本发明一般涉及通过原子层沉积来增强在衬底上沉积贵金属薄膜的方法。 使用气态卤化物或金属有机化合物进行处理减少了在特定表面上沉积贵金属的孵育时间。 该方法可用于促进选择性沉积。 例如，可以通过用卤化物反应物预处理来提高贵金属在高k材料上相对于绝缘体的选择性沉积。 此外，可以使用卤化物处理以避免沉积在反应室的石英壁上。

公开(公告)号：US20130196502A1

公开(公告)日：2013-08-01

申请号：US13708863

申请日：2012-12-07

Applicant: ASM International. N.V.

Inventor： Suvi P. Haukka ,  Antti Niskanen

IPC: H01L21/768

CPC classification number: H01L21/7685 ,  C23C16/04 ,  C23C16/14 ,  C23C16/45536 ,  C23C16/45553 ,  H01L21/02068 ,  H01L21/28518 ,  H01L21/28562 ,  H01L21/28568 ,  H01L21/3105 ,  H01L21/76826 ,  H01L21/76849 ,  H01L21/76864 ,  H01L21/76867 ,  H01L21/76883 ,  H01L21/76886 ,  H01L21/76889 ,  H01L23/53238

Abstract: Metallic layers can be selectively deposited on one surface of a substrate relative to a second surface of the substrate. In some embodiments, the metallic layers are selectively deposited on copper instead of insulating or dielectric materials. In some embodiments, a first precursor forms a layer on the first surface and is subsequently reacted or converted to form a metallic layer. The deposition temperature may be selected such that a selectivity of above about 50% or even about 90% is achieved.

Abstract translation: 金属层可以相对于基板的第二表面选择性沉积在衬底的一个表面上。 在一些实施例中，金属层选择性地沉积在铜上而不是绝缘或介电材料。 在一些实施方案中，第一前体在第一表面上形成一层，随后反应或转化以形成金属层。 可以选择沉积温度使得达到高于约50％或甚至约90％的选择性。

公开(公告)号：US20130115763A1

公开(公告)日：2013-05-09

申请号：US13667541

申请日：2012-11-02

Applicant: ASM International. N.V.

Inventor： Noboru Takamure ,  Atsuki Fukazawa ,  Hideaki Fukuda ,  Antti Niskanen ,  Suvi Haukka ,  Ryu Nakano ,  Kunitoshi Namba

IPC: H01L21/26 ,  H01L21/31

CPC classification number: H01L21/02321 ,  H01L21/02129 ,  H01L21/02164 ,  H01L21/02208 ,  H01L21/02219 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/2225 ,  H01L21/2255 ,  H01L21/324 ,  H01L29/66803

Abstract: The present disclosure relates to the deposition of dopant films, such as doped silicon oxide films, by atomic layer deposition processes. In some embodiments, a substrate in a reaction space is contacted with pulses of a silicon precursor and a dopant precursor, such that the silicon precursor and dopant precursor adsorb on the substrate surface. Oxygen plasma is used to convert the adsorbed silicon precursor and dopant precursor to doped silicon oxide.

公开(公告)号：US08399344B2

公开(公告)日：2013-03-19

申请号：US12898911

申请日：2010-10-06

Applicant: Dieter Pierreux ,  Vladimir Machkaoutsan ,  Jan Willem Maes

Inventor： Dieter Pierreux ,  Vladimir Machkaoutsan ,  Jan Willem Maes

IPC: H01L21/28

CPC classification number: H01L29/513 ,  H01L21/28194 ,  H01L29/517

Abstract: A method for fabricating a semiconductor device comprising a gate stack of a gate dielectric and a gate electrode, the method including forming a gate dielectric layer over a semiconductor substrate the gate dielectric layer being a metal oxide or semimetal oxide having a first electronegativity; forming a dielectric VT adjustment layer, the dielectric VT adjustment layer being a metal oxide or semimetal oxide having a second electronegativity; and forming a gate electrode over the gate dielectric layer and the VT adjustment layer; wherein the Effective Work Function of said gate stack is tuned to a desired value by tuning the thickness and composition of the dielectric VT adjustment layer and wherein the second electronegativity value is higher than both the first electronegativity value and the electronegativity of Al2O3.

Abstract translation: 一种用于制造半导体器件的方法，包括栅极电介质和栅电极的栅极堆叠，所述方法包括在半导体衬底上形成具有第一电负性的金属氧化物或半金属氧化物的栅极介电层; 形成电介质VT调整层，电介质VT调整层是具有第二电负性的金属氧化物或半金属氧化物; 以及在所述栅极电介质层和所述VT调整层上形成栅电极; 其中所述栅极叠层的有效功函数通过调谐介电VT调整层的厚度和组成而被调谐到期望值，并且其中第二电负性值高于第一电负性值和Al 2 O 3的电负性。

公开(公告)号：US20130065352A1

公开(公告)日：2013-03-14

申请号：US13669550

申请日：2012-11-06

Applicant: ASM INTERNATIONAL N.V.

Inventor： Chris G. M. de Ridder ,  Klaas P. Boonstra ,  Adriaan Garssen ,  Frank Huussen

IPC: H01L31/0216

CPC classification number: H01L21/67303 ,  C23C16/45546 ,  C23C16/4587 ,  F27B17/0025 ,  F27D5/0037 ,  H01L21/67109 ,  H01L21/67313 ,  H01L21/67757 ,  H01L31/1864 ,  H01L31/1876 ,  Y02E10/547 ,  Y02P70/521

Abstract: A method for processing solar cells comprising: providing a vertical furnace to receive an array of mutually spaced circular semiconductor wafers for integrated circuit processing; composing a process chamber loading configuration for solar cell substrates, wherein a size of the solar cell substrates that extends along a first surface to be processed is smaller than a corresponding size of the circular semiconductor wafers, such that multiple arrays of mutually spaced solar cell substrates can be accommodated in the process chamber, loading the solar cell substrates into the process chamber; subjecting the solar cell substrates to a process in the process chamber.

Abstract translation: 一种用于处理太阳能电池的方法，包括：提供垂直炉以接收用于集成电路处理的相互间隔开的圆形半导体晶片阵列; 构成用于太阳能电池基板的处理室装载构造，其中沿着待处理的第一表面延伸的太阳能电池基板的尺寸小于圆形半导体晶片的对应尺寸，使得相互间隔开的太阳能电池基板的多个阵列 可以容纳在处理室中，将太阳能电池基板装载到处理室中; 对太阳能电池基板进行处理室中的处理。

公开(公告)号：US20120329208A1

公开(公告)日：2012-12-27

申请号：US13504079

申请日：2010-10-25

Applicant: Viljami Pore ,  Timo Hatanpää ,  Mikko Ritala ,  Markku Leskelä

Inventor： Viljami Pore ,  Timo Hatanpää ,  Mikko Ritala ,  Markku Leskelä

IPC: H01L21/06 ,  H01L21/31

CPC classification number: C23C16/45553 ,  C23C16/18 ,  C23C16/305 ,  C23C16/4408 ,  C23C16/45555 ,  H01L21/02521 ,  H01L21/02538 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/02551 ,  H01L21/0262 ,  H01L45/06 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1616

Abstract: Atomic layer deposition (ALD) processes for forming Group VA element containing thin films, such as Sb, Sb—Te, Ge—Sb and Ge—Sb—Te thin films are provided, along with related compositions and structures. Sb precursors of the formula Sb(SiR1R2R3)3 are preferably used, wherein R1, R2, and R3 are alkyl groups. As, Bi and P precursors are also described. Methods are also provided for synthesizing these Sb precursors. Methods are also provided for using the Sb thin films in phase change memory devices.

Abstract translation: 提供了用于形成含有Sb，Sb-Te，Ge-Sb和Ge-Sb-Te薄膜的含VA薄膜的原子层沉积（ALD）工艺，以及相关组合物和结构。 优选使用Sb（SiR1R2R3）3的Sb前体，其中R1，R2和R3是烷基。 As，Bi和P前体也被描述。 还提供了用于合成这些Sb前体的方法。 还提供了在相变存储器件中使用Sb薄膜的方法。