公开(公告)号：US5915191A

公开(公告)日：1999-06-22

申请号：US794061

申请日：1997-02-04

申请人： Young Kwon Jun

发明人： Young Kwon Jun

IPC分类号： H01L21/316 ,  H01L21/76 ,  H01L21/762

CPC分类号： H01L21/76216 ,  H01L21/76227 ,  H01L21/76237

摘要： A method for the fabrication of a semiconductor device is characterized by a series of steps comprising successively forming a trench in a field region of monosilicon substrate and forming an oxidation-preventive layer and a silicon layer in the trench, and oxidizing the silicon layer into a field oxide film to produce a channel stop region beneath the trench in the substrate. The method alternatively comprises forming a trench having a small pattern in a field region of a monosilicon substrate, sequentially forming an oxidation-preventive layer and a silicon layer on the surface of the trench, and oxidizing the silicon layer and the substrate of a field region having a large pattern size, at the same time, to produce a field oxide film and channel stop diffusion regions below both the trench and the field oxide film having a large pattern. Such channel stop diffusion regions contribute to minimizing the redistribution of channel stop ions in the monosilicon substrate below both the trench and the field oxide film having a large pattern. In addition, the channel stop diffusion region restrains stress caused by oxidation of the monosilicon substrate and improves the insulation properties of the field region.

摘要翻译： 制造半导体器件的方法的特征在于一系列步骤，包括在单硅衬底的场区域中连续地形成沟槽，并在沟槽中形成氧化防止层和硅层，并将硅层氧化成 场氧化物膜以在衬底中的沟槽下方产生沟道停止区。 该方法或者包括在单硅衬底的场区域中形成具有小图案的沟槽，在沟槽的表面上依次形成氧化防止层和硅层，并且氧化硅层和衬底的场区域 具有大的图案尺寸，同时产生具有大图案的沟槽和场氧化物膜下面的场氧化物膜和沟道阻挡扩散区域。 这种通道阻挡扩散区域有助于最小化在具有大图案的沟槽和场氧化物膜下面的单硅衬底中的通道停止离子的再分布。 此外，通道阻挡扩散区域抑制由单硅衬底的氧化引起的应力，并且改善了场区域的绝缘性能。

公开(公告)号：US5905688A

公开(公告)日：1999-05-18

申请号：US30844

申请日：1998-02-26

申请人： Jong-Hoon Park

发明人： Jong-Hoon Park

IPC分类号： G11C11/41 ,  G11C11/413 ,  G11C11/417 ,  G11C29/06 ,  G11C29/50 ,  G11C7/00

CPC分类号： G11C11/417 ,  G11C29/50 ,  G11C11/41

摘要： A power down circuit for a memory device is provided that includes a burn-in voltage detector to generate a burn-in voltage detecting signal to control a power down signal when a burn-in voltage reaches a predetermined level. The power down circuit enhances a burn-in function by operating the memory cells and peripheral circuits for a relatively long time at a high level voltage when a burn-in is performed on the memory device with an auto power down function. Thus, the memory device reliability is also enhanced. The memory device includes a power down timer for generating a power down signal to control an input/output operation of a memory cell in response to a plurality of address transition detecting signals, a plurality of data input detecting signals, a chip select detecting signal, a write mode detecting signal and the burn-in voltage detecting signal.

摘要翻译： 提供一种用于存储器件的掉电电路，其包括老化电压检测器，以在老化电压达到预定电平时产生老化电压检测信号，以控制掉电信号。 断电电路通过在具有自动关机功能的存储器件上进行老化时以高电平电压操作存储器单元和外围电路相当长的时间来增强老化功能。 因此，存储器件的可靠性也得到提高。 该存储装置包括一个断电定时器，用于响应于多个地址转换检测信号，多个数据输入检测信号，芯片选择检测信号，产生掉电信号来控制存储器单元的输入/输出操作， 写入模式检测信号和老化电压检测信号。

公开(公告)号：US5905674A

公开(公告)日：1999-05-18

申请号：US42022

申请日：1998-03-13

申请人： Woong-Lim Choi

发明人： Woong-Lim Choi

IPC分类号： G11C17/00 ,  G11C11/56 ,  G11C16/00 ,  G11C16/02 ,  G11C16/04 ,  G11C16/34 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C11/34

CPC分类号： G11C16/3486 ,  G11C11/5621 ,  G11C11/5628 ,  G11C16/0416 ,  G11C16/0441 ,  G11C16/3468 ,  G11C16/3481 ,  G11C2211/5613 ,  G11C2211/5624

摘要： A nonvolatile memory cell includes a floating gate; a programming region, having a first current path to the floating gate, for programming by providing charge carriers to the floating gate through the first current path or extracting charge carriers stored in the floating gate; and a verification region, having a second current path separated from the first current path, for verifying the charge amount of the floating gate through the second current path during programming.

摘要翻译： 非易失性存储单元包括浮动栅极; 编程区域，具有到浮动栅极的第一电流路径，用于通过经由第一电流路径向浮动栅极提供电荷载流体或者提取存储在浮动栅极中的电荷载流子来编程; 以及具有与第一电流路径分离的第二电流路径的验证区域，用于在编程期间验证通过第二电流路径的浮置栅极的电荷量。

公开(公告)号：US5903169A

公开(公告)日：1999-05-11

申请号：US775951

申请日：1997-01-03

申请人： Bai-Sun Kong

发明人： Bai-Sun Kong

IPC分类号： G11C11/41 ,  G11C7/00 ,  G11C11/412 ,  H03K3/356 ,  H03K19/00 ,  H03K19/0944 ,  H03K19/096 ,  H03K19/173 ,  H03K19/21

CPC分类号： G11C11/412 ,  H03K19/0019 ,  H03K19/0963 ,  H03K19/1738 ,  H03K19/215 ,  H03K3/356147 ,  G06F2207/3884

摘要： A storage element for a semiconductor device in accordance with preferred embodiments exhibit less noise and consumes less power with faster speed. A first circuit maintains a first storage node at a same signal level of a previous state when an input signal at an input electrode transits from one of (i) first signal level to second signal level and (ii) third signal level to second signal level. The first circuit includes a first plurality of transistors coupled to the input electrode, and a first pair of transistors coupled to said first plurality of transistors and coupled to each other at the first storage node. A second circuit, coupled to said first circuit, changes a condition of said first storage node to one of (i) first signal level when the input signal transits from the second signal level to the first signal level and (ii) third signal level when the input signal transits from the second signal level to the third signal level.

摘要翻译： 根据优选实施例的用于半导体器件的存储元件表现出较小的噪声并且以更快的速度消耗更少的功率。 当输入电极的输入信号从（i）第一信号电平之一转换到第二信号电平时，第一电路将先前状态的第一存储节点维持在相同的信号电平，以及（ii）第三信号电平转换到第二信号电平 。 第一电路包括耦合到输入电极的第一多个晶体管，以及耦合到所述第一多个晶体管并在第一存储节点处彼此耦合的第一对晶体管。 当所述输入信号从所述第二信号电平转换到所述第一信号电平时，耦合到所述第一电路的第二电路将所述第一存储节点的状态改变为（i）第一信号电平之一，以及（ii）第三信号电平， 输入信号从第二信号电平转换到第三信号电平。

公开(公告)号：US5903013A

公开(公告)日：1999-05-11

申请号：US751240

申请日：1996-11-18

申请人： Sung Kge Park

发明人： Sung Kge Park

IPC分类号： H01L21/336 ,  H01L29/786 ,  H01L29/04 ,  H01L31/036 ,  H01L31/0376 ,  H01L31/20

CPC分类号： H01L29/78624

摘要： A thin film transistor includes a substrate, a gate electrode formed on the substrate, and including opposing edge portions and a middle portion. An insulating film is formed on the surface of the gate electrode having a greater thickness on one of the gate edge portions. An active region is formed on the surface of the insulating film and the exposed substrate. The active region includes an off-set region, a channel region, a source region, and a drain region.

摘要翻译： 薄膜晶体管包括基板，形成在基板上的栅电极，并且包括相对的边缘部分和中间部分。 在栅极边缘部分之一上在栅电极的表面上形成绝缘膜，其厚度较大。 在绝缘膜和暴露的基板的表面上形成有源区。 有源区域包括偏移区域，沟道区域，源极区域和漏极区域。

公开(公告)号：US5900656A

公开(公告)日：1999-05-04

申请号：US6445

申请日：1998-01-13

申请人： Keun Hyung Park

发明人： Keun Hyung Park

IPC分类号： G11C16/04 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11521 ,  G11C16/0416 ,  H01L27/115 ,  H01L29/78391 ,  H01L29/7883

摘要： A semiconductor memory device includes a semiconductor substrate of a first conductivity-type, a first electrode formed on the semiconductor substrate for charging/discharging charges, a second electrode formed on the first electrode for controlling charging/discharging and data reading/writing of the first electrode, and a charge input/output stage formed on the semiconductor substrate on at least one side of the second electrode for supplying charges.

摘要翻译： 半导体存储器件包括第一导电类型的半导体衬底，形成在用于充电/放电的半导体衬底上的第一电极，形成在用于控制充电/放电的第一电极上的第二电极以及第一电极的数据读/写 电极和电荷输入/输出级，形成在第二电极的至少一侧的半导体衬底上，用于提供电荷。

公开(公告)号：US5900655A

公开(公告)日：1999-05-04

申请号：US848555

申请日：1997-04-28

申请人： Jin Seop Shim

发明人： Jin Seop Shim

IPC分类号： H01L27/14 ,  H01L21/304 ,  H01L27/146 ,  H01L27/148 ,  H01L31/0216 ,  H01L29/768

CPC分类号： H01L27/14627 ,  H01L27/14868 ,  H01L31/02162

摘要： A charge coupled device and a method of manufacturing a charged coupled device includes a semiconductor substrate, a plurality of photoelectrical conversion cells formed in the semiconductor substrate in a matrix form, a plurality of vertical charge coupled device regions formed between the plurality of photoelectrical conversion cells, a plurality of stripe layers formed on the semiconductor substrate and corresponding to the plurality of vertical charge coupled device regions, and a plurality of microlenses formed on the semiconductor substrate and corresponding to the plurality of photoelectrical conversion cells.

摘要翻译： 电荷耦合器件和制造充电耦合器件的方法包括半导体衬底，以矩阵形式形成在半导体衬底中的多个光电转换单元，形成在多个光电转换单元之间的多个垂直电荷耦合器件区域 形成在所述半导体衬底上并对应于所述多个垂直电荷耦合器件区域的多个条纹层以及形成在所述半导体衬底上并对应于所述多个光电转换单元的多个微透镜。

公开(公告)号：US5897369A

公开(公告)日：1999-04-27

申请号：US714369

申请日：1996-09-16

申请人： Young Kwon Jun

发明人： Young Kwon Jun

IPC分类号： H01L21/28 ,  H01L21/768 ,  H01L23/48 ,  H01L23/522 ,  H01L21/441

CPC分类号： H01L21/76834 ,  H01L21/76831 ,  H01L21/76847 ,  H01L21/76876 ,  H01L21/76877 ,  H01L21/76885

摘要： A method for forming an interconnection of a semiconductor device, includes the steps of forming an insulating layer on a substrate on which a lower conductive layer is formed, selectively removing the insulating layer to form a first connecting hole and a second connecting hole for the pattern of an upper conductive layer, growing a first conductive material in the first connecting hole to form a buried plug and then depositing a second conductive material on the surface of the insulating layer to form a barrier layer, and depositing a third conductive material on the barrier layer to fill the second connecting hole and then patterning it to form an upper conductive layer.

摘要翻译： 一种用于形成半导体器件的互连的方法包括以下步骤：在其上形成下导电层的衬底上形成绝缘层，选择性地去除绝缘层以形成用于图案的第一连接孔和第二连接孔 在第一连接孔中生长第一导电材料以形成掩埋塞，然后在绝缘层的表面上沉积第二导电材料以形成阻挡层，以及将第三导电材料沉积在阻挡层上 层以填充第二连接孔，然后将其图案化以形成上导电层。

公开(公告)号：US5896323A

公开(公告)日：1999-04-20

申请号：US900340

申请日：1997-07-25

申请人： Yi Hwan Park ,  Hyun Soo Shin

发明人： Yi Hwan Park ,  Hyun Soo Shin

IPC分类号： G11C11/41 ,  G11C7/10 ,  G11C11/407 ,  G11C11/409 ,  G11C11/413 ,  G11C16/04

CPC分类号： G11C7/1057 ,  G11C7/1051 ,  G11C7/106

摘要： A data output control circuit for a semiconductor memory device sequentially transmits input data via a main amplifier controlled by an address transition detecting signal, a multiplex/latch unit, a data output buffer and an output operator. The data output control circuit prevents false data output, which also improves data processing speed by using a control signal. The data output control circuit includes an output control unit that converts an address transition detecting signal into a kill signal. The kill signal is applied to the data output buffer to cause the output operator to generate a zero level signal based on the address transition detecting signal. The data output control circuit enables the output operator to generate a zero level signal by applying the kill signal to the data output buffer when the transition of an address signal is detected. Accordingly, an interval for a data reversal or a full swing is prevented to enhance data processing speed and reduce current consumption.

摘要翻译： 用于半导体存储器件的数据输出控制电路通过由地址转换检测信号控制的主放大器，多路复用/锁存单元，数据输出缓冲器和输出运算器顺序发送输入数据。 数据输出控制电路防止伪数据输出，这也通过使用控制信号来提高数据处理速度。 数据输出控制电路包括将地址转换检测信号转换为停止信号的输出控制单元。 杀死信号被施加到数据输出缓冲器，以使得输出操作者基于地址转换检测信号产生零电平信号。 当检测到地址信号的转换时，数据输出控制电路使得输出操作者能够通过将数据输出缓冲器应用到数据输出缓冲器来产生零电平信号。 因此，防止数据反转或全摆动的间隔以提高数据处理速度并减少电流消耗。

公开(公告)号：US5895258A

公开(公告)日：1999-04-20

申请号：US774801

申请日：1996-12-30

申请人： Du-Heon Song

发明人： Du-Heon Song

IPC分类号： H01L21/316 ,  H01L21/265 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L21/823418 ,  H01L21/76218

摘要： A semiconductor fabrication method for forming an insulation film and a first anti-oxidation film sequentially on a substrate which is sectioned into each of a peri region and a cell region. An active pattern is formed in the cell region and a first field ion-implanted region in a first conductive well of the cell region. Side wall spacers are formed on each side wall of the active pattern in the cell region. An active pattern is formed in the peri region by selectively etching the first anti-oxidation film and the insulation film so as to expose a certain surface portion of the peri region substrate therethrough. A first field ion-implanting region is formed in a first conductive well of the peri region by ion-implanting highly concentrated first conductive impurities through the exposed substrate and a second field ion-implanted region in a second conductive well of the peri region. Lastly, a field oxide layer created using a field oxidation process after removing the first anti-oxidation film, the insulation film and the side wall spacers. The method beings by forming a semiconductor device which eliminates double hump phenomenon, decreases leakage current and lowers stand-by current to improve the operating properties of the device.

摘要翻译： 一种半导体制造方法，用于在分为围区域和单元区域中的每一个基板上依次形成绝缘膜和第一抗氧化膜。 在单元区域中形成有源图案和在单元区域的第一导电孔中的第一场离子注入区域。 在电池区域中的活性图案的每个侧壁上形成侧壁间隔物。 通过选择性地蚀刻第一抗氧化膜和绝缘膜，在周边区域形成有源图案，以使周边区域基板的某一表面部分暴露出来。 第一场离子注入区通过离子注入高度浓缩的第一导电杂质通过暴露的衬底和在围绕区的第二导电阱中的第二场离子注入区形成在围绕区的第一导电阱中。 最后，在除去第一抗氧化膜，绝缘膜和侧壁间隔物之后，使用场氧化工艺制造的场氧化物层。 通过形成消除双峰现象的半导体器件的方法，减少漏电流并降低待机电流以改善器件的工作特性。