公开(公告)号：US08941616B2

公开(公告)日：2015-01-27

申请号：US14166054

申请日：2014-01-28

申请人： Japan Display Inc. ,  Panasonic Liquid Crystal Display Co., Ltd.

发明人： Masahiro Teramoto

IPC分类号： G06F3/044 ,  G06F3/041

CPC分类号： G06F3/0416 ,  G06F3/0412 ,  G06F3/044 ,  G06F3/047 ,  G06F2203/04103 ,  G06F2203/04111 ,  H01L21/0425 ,  H01L21/044 ,  H01L21/311 ,  H01L21/3213 ,  H05K3/0017

摘要： A touch panel includes a substrate, a plurality of first electrodes extending in a first direction on the substrate and being disposed in parallel in a second direction intersecting the first direction, and a plurality of second electrodes intersecting the plurality of first electrodes, extending in the second direction, and being disposed in parallel in the first direction. Each of the plurality of first electrodes includes a first portion and a second portion with the second portion of first electrode and the second electrode being made of a first conductive film, and the first portion of the first electrode being made of a second conductive film.

摘要翻译： 触摸面板包括基板，在基板上沿第一方向延伸并且沿与第一方向相交的第二方向平行设置的多个第一电极以及与多个第一电极相交的多个第二电极， 第二方向，并且沿第一方向平行设置。 多个第一电极中的每一个包括第一部分和第二部分，第一部分由第一电极和第二电极构成，第一电极的第一部分由第二导电膜制成。

公开(公告)号：US20140377953A1

公开(公告)日：2014-12-25

申请号：US14281606

申请日：2014-05-19

申请人： Micron Technology, Inc.

发明人： Dinesh Chopra

IPC分类号： H01L21/3213

CPC分类号： H01L21/3213 ,  B23H5/08 ,  C25F3/02 ,  C25F3/30 ,  C25F7/00 ,  H01L21/32115 ,  H01L21/32125 ,  H01L21/32134 ,  H01L21/7684

摘要： A method and apparatus for simultaneously removing conductive materials from a microelectronic substrate. A method in accordance with one embodiment of the invention includes contacting a surface of a microelectronic substrate with an electrolytic liquid, the microelectronic substrate having first and second different conductive materials. The method can further include controlling a difference between a first open circuit potential of the first conducive material and a second open circuit potential of the second conductive material by selecting a pH of the electrolytic liquid. The method can further include simultaneously removing at least portions of the first and second conductive materials by passing a varying electrical signal through the electrolytic liquid and the conductive materials. Accordingly, the effects of galvanic interactions between the two conductive materials can be reduced and/or eliminated.

摘要翻译： 一种用于从微电子衬底同时去除导电材料的方法和装置。 根据本发明的一个实施例的方法包括使微电子衬底的表面与电解液接触，微电子衬底具有第一和第二不同的导电材料。 该方法还可以包括通过选择电解液的pH来控制第一导电材料的第一开路电位和第二导电材料的第二开路电位之间的差。 该方法还可以包括通过使变化的电信号通过电解液和导电材料同时去除第一和第二导电材料的至少一部分。 因此，可以减少和/或消除两种导电材料之间的电偶相互作用的影响。

公开(公告)号：US20130234301A1

公开(公告)日：2013-09-12

申请号：US13417299

申请日：2012-03-11

申请人： Chih-Jung Wang ,  Tong-Yu Chen

发明人： Chih-Jung Wang ,  Tong-Yu Chen

IPC分类号： H01L29/02 ,  H01L21/32

CPC分类号： H01L27/11 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/28123 ,  H01L21/3213 ,  H01L21/823431 ,  H01L21/845

摘要： A method for fabricating a patterned structure in a semiconductor device is provided. First, a substrate with a first region and a second region is provided. Then, a plurality of sacrificial patterns is respectively formed within the first region and the second region. A first spacer is then formed on the sidewalls of each of the sacrificial patterns followed by forming a mask layer to cover the sacrificial patterns located within the first region. Finally, the first spacer exposed from the mask layer is trimmed to be a second spacer and the mask layer is then removed.

摘要翻译： 提供了一种在半导体器件中制造图案化结构的方法。 首先，提供具有第一区域和第二区域的基板。 然后，分别在第一区域和第二区域内形成多个牺牲图案。 然后在每个牺牲图案的侧壁上形成第一间隔物，随后形成掩模层以覆盖位于第一区域内的牺牲图案。 最后，将从掩模层露出的第一间隔物修剪成第二间隔物，然后除去掩模层。

公开(公告)号：US20130153990A1

公开(公告)日：2013-06-20

申请号：US13710415

申请日：2012-12-10

申请人： SK hynix Inc.

发明人： Byoung Hoon LEE ,  Chang Moon LIM

IPC分类号： H01L29/66 ,  H01L29/78

CPC分类号： H01L27/10885 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/26586 ,  H01L21/30625 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/3213 ,  H01L27/0207 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10888 ,  H01L29/66666 ,  H01L29/7827

摘要： In a semiconductor device and a method for manufacturing the same, a pillar pattern is formed in an alternating pattern and a one side contact (OSC) is formed without using a tilted ion implantation process or a mask, resulting in formation of a vertical gate. The semiconductor device includes an alternating or zigzag-type pillar pattern formed over a semiconductor substrate, a first hole formed between pillars of the pillar pattern, a passivation layer formed over a sidewall of the first hole, a second hole formed by partially etching a lower part of the first hole, a bit line formed in the second hole, and a contact formed at a lower part of the pillar pattern.

公开(公告)号：US20090239042A1

公开(公告)日：2009-09-24

申请号：US12052980

申请日：2008-03-21

申请人： Kanti JAIN ,  Junghun CHAE

发明人： Kanti JAIN ,  Junghun CHAE

IPC分类号： B32B3/10 ,  B29C35/08 ,  B05D5/12 ,  C23C16/453 ,  C23C16/50 ,  G03F7/20

CPC分类号： H01L21/3213 ,  B23K26/0006 ,  B23K26/18 ,  B23K26/352 ,  B23K26/40 ,  B23K2103/08 ,  B23K2103/42 ,  B23K2103/50 ,  B23K2103/52 ,  B23K2103/56 ,  B81C1/00634 ,  B82Y20/00 ,  B82Y30/00 ,  G03F7/202 ,  Y10T428/24802

摘要： This invention provides photoablation—based processing techniques and materials strategies for making, assembling and integrating patterns of materials for the fabrication of electronic, optical and opto-electronic devices. Processing techniques of the present invention enable high resolution and/or large area patterning and integration of porous and/or nano- or micro-structured materials comprising active or passive components of a range of electronic devices, including integrated circuits (IC), microelectronic and macroelectronic systems, microfluidic devices, biomedical devices, sensing devices and device arrays, and nano- and microelectromechanical systems.

摘要翻译： 本发明提供了用于制造，组装和集成用于制造电子，光学和光电子器件的材料的图案的基于光消息的处理技术和材料策略。 本发明的加工技术能够实现高分辨率和/或大面积图案化和多孔和/或纳米或微结构材料的整合，包括一系列电子器件的有源或无源元件，包括集成电路（IC），微电子和 宏观电子系统，微流体装置，生物医学装置，感测装置和装置阵列以及纳米和微机电系统。

公开(公告)号：US20070134921A1

公开(公告)日：2007-06-14

申请号：US11302769

申请日：2005-12-14

申请人： Ruiqi Tian ,  Willard Conley ,  Mehul Shroff

发明人： Ruiqi Tian ,  Willard Conley ,  Mehul Shroff

IPC分类号： H01L21/302

CPC分类号： H01L21/31144 ,  H01L21/0334 ,  H01L21/31053 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/32139 ,  Y10S438/926

摘要： A method for forming a semiconductor device includes providing a plurality of features in a layout, selecting critical features from the plurality of features, placing a first plurality of short-range dummy etch features in the layout at a first distance from the critical features to increase the feature density near the critical features, wherein each of the first plurality of short-range dummy etch features has a first width, removing at least one of the first plurality of short-range dummy etch features from the layout that will subsequently interfere with the electrical performance of at least one active feature so that a second plurality of short-range dummy etch features remains, and using the layout to pattern a layer on a semiconductor substrate.

摘要翻译： 一种用于形成半导体器件的方法包括在布局中提供多个特征，从多个特征中选择关键特征，将布置中的第一多个短距离虚拟蚀刻特征放置在离关键特征的第一距离处以增加 临界特征附近的特征密度，其中第一多个短距离虚拟蚀刻特征中的每一个具有第一宽度，从布局去除第一多个短程虚拟蚀刻特征中的至少一个，随后将干扰 至少一个有源特征的电性能，使得第二多个短距离虚拟蚀刻特征保留，并且使用布局来在半导体衬底上图案化。

公开(公告)号：US20020160594A1

公开(公告)日：2002-10-31

申请号：US10121542

申请日：2002-04-12

发明人： Tetsuya Hayashi ,  Toshifumi Takahashi

IPC分类号： H01L021/336 ,  H01L021/3205 ,  H01L021/4763

CPC分类号： H01L21/304 ,  H01L21/3213 ,  H01L29/6659 ,  Y10S438/928

摘要： In order to suppress generation of waste matter which results from removing a backside film formed by growing a film on both surfaces of a semiconductor substrate and thereby attain satisfactorily high yield and productivity, on a semiconductor substrate 301, a polycrystalline silicon film 303 is formed through double-sided growth, and only on the obverse surface of the semiconductor substrate 301 a silicide film 304 is formed thereon, and then those polycrystalline silicon film 303 and silicide film 304 are worked into shape to form gate electrodes 303a. After that, on the semiconductor substrate 301, an insulating film for sidewall formation is formed to cover the gate electrodes 303a through double-sided growth, and the insulating film for sidewall formation formed on the obverse surface of the semiconductor substrate 301 is etched to form sidewall films. Only on the obverse surface side of the semiconductor substrate 301, an interlayer insulating film is formed to cover the gate electrodes 303a, and thereafter the polycrystalline silicon film 303 and the insulating film for sidewall formation, both of which are formed on the reverse surface side of the semiconductor substrate 301, as well as a part of said semiconductor substrate 301 in depth from the reverse surface are removed by grinding, whereby a semiconductor device is fabricated.

摘要翻译： 为了抑制由于通过在半导体衬底的两个表面上生长膜形成的背面膜而产生的废物的产生，从而获得令人满意的高产率和生产率，在半导体衬底301上形成多晶硅膜303， 双面生长，并且仅在半导体衬底301的正面上形成硅化物膜304，然后将那些多晶硅膜303和硅化物膜304加工成形状以形成栅电极303a。 之后，在半导体衬底301上形成用于侧壁形成的绝缘膜，以通过双面生长覆盖栅电极303a，并且蚀刻形成在半导体衬底301的正面上的侧壁形成用绝缘膜以形成 侧壁膜。 仅在半导体基板301的正面侧，形成层间绝缘膜，覆盖栅电极303a，之后形成在反面侧的多晶硅膜303和侧壁形成用绝缘膜 的半导体衬底301以及远离反面的深度的半导体衬底301的一部分通过研磨去除，由此制造半导体器件。

公开(公告)号：US06426288B1

公开(公告)日：2002-07-30

申请号：US09382218

申请日：1999-08-24

申请人： Scott G. Meikle

发明人： Scott G. Meikle

IPC分类号： H01L21302

CPC分类号： H01L21/321 ,  H01L21/3213 ,  H01L21/32134

摘要： A method for removing a portion of an upper layer of one material from an underlying layer of another material to form a uniformly planar surface on a semiconductor wafer. In accordance with one embodiment of the invention, an upper section of the upper layer is etched to an intermediate point in the upper layer. The etching step removes the upper section of the upper layer and leaves only a lower section of the upper layer on the wafer. The lower section of the upper layer is then planarized to a final endpoint. The etching step preferably moves the majority of the upper layer from the wafer so that the remaining portion of the upper layer is thick enough to allow the planarization step to produce a uniformly planar finished surface on the wafer.

摘要翻译： 一种用于从另一种材料的下层去除一种材料的上层的一部分以在半导体晶片上形成均匀平坦的表面的方法。 根据本发明的一个实施例，上层的上部被蚀刻到上层的中间点。 蚀刻步骤去除上层的上部并且仅在晶片上留下上层的下部。 然后将上层的下部平面化为最终端点。 蚀刻步骤优选地从晶片移动上层的大部分，使得上层的剩余部分足够厚以允许平坦化步骤在晶片上产生均匀平面的成品表面。

公开(公告)号：US06407443B2

公开(公告)日：2002-06-18

申请号：US09886355

申请日：2001-06-20

申请人： Yong Chen ,  R. Stanley Williams

发明人： Yong Chen ,  R. Stanley Williams

IPC分类号： H01L21336

CPC分类号： B82Y10/00 ,  B82Y40/00 ,  G03F7/0002 ,  H01L21/3213 ,  H01L21/76838 ,  Y10S977/887

摘要： A method for forming a platen useful for forming nanoscale wires for device applications comprises: (a) providing a substrate having a major surface; (b) forming a plurality of alternating layers of two dissimilar materials on the substrate to form a stack having a major surface parallel to that of the substrate; (c) cleaving the stack normal to its major surface to expose the plurality of alternating layers; and (d) etching the exposed plurality of alternating layers to a chosen depth using an etchant that etches one material at a different rate than the other material to thereby provide the surface with extensive strips of indentations and form the platen useful for molding masters for nano-imprinting technology. The pattern of the platen is then imprinted into a substrate comprising a softer material to form a negative of the pattern, which is then used in further processing to form nanowires. The nanoscale platen thus comprises a plurality of alternating layers of the two dissimilar materials, with the layers of one material etched relative the layers of the other material to form indentations of the one material. The platen is then oriented such that the indentations are perpendicular to a surface to be imprinted.

摘要翻译： 用于形成用于形成用于器件应用的纳米线的压板的方法包括：（a）提供具有主表面的衬底; （b）在所述基板上形成两个不同材料的多个交替层，以形成具有平行于所述基板的主表面的堆叠; （c）将堆叠垂直于其主表面分开以暴露多个交替层; 以及（d）使用蚀刻剂以与其它材料不同的速率蚀刻一种材料的蚀刻剂将暴露的多个交替层蚀刻到所选择的深度，从而为表面提供大量的凹痕，并形成用于成型纳米级的母料的压板 打印技术 然后将压板的图案印刷到包括较软材料的基材中以形成图案的负片，然后将其用于进一步加工以形成纳米线。 纳米级压板因此包括两个不同材料的多个交替层，一个材料的层相对于另一个材料的层被蚀刻以形成该材料的凹陷。 然后将压板定向成使得凹陷垂直于待印刷的表面。

公开(公告)号：US20020014653A1

公开(公告)日：2002-02-07

申请号：US09528406

申请日：2000-03-17

发明人： Emilo Camerlenghi ,  Elio Colabella ,  Luca Pividori ,  Adriana Rebora

IPC分类号： H01L029/76

CPC分类号： H01L27/11521 ,  H01L21/3213 ,  H01L21/76838

摘要： Self-aligned etching process for providing a plurality of mutually parallel word lines in a first conducting layer deposited over a planarized architecture obtained starting from a semiconductor substrate on which is provided a plurality of active elements extending along separate parallel lines e.g., memory cell bit lines and comprising gate regions made up of a first conducting layer, an intermediate dielectric layer and a second conducting layer with said regions being insulated from each other by insulation regions to form said architecture with said word lines being defined photolithographically by protective strips implemented by means of: a vertical profile etching for complete removal from the unprotected areas of the first conducting layer of the second conducting layer and of the intermediate dielectric layer respectively, and a following isotropic etching of the first conducting layer.

摘要翻译： 自对准蚀刻工艺，用于在由半导体衬底开始沉积的第一导电层中沉积的第一导电层中提供多个相互平行的字线，所述半导体衬底上设置有沿着分离的并行线延伸的多个有源元件，例如存储器单元位线 并且包括由第一导电层，中间电介质层和第二导电层构成的栅极区，其中所述区域通过绝缘区域彼此绝缘以形成所述结构，所述字线通过防护带光刻地限定， ：用于从第二导电层和中间介电层的第一导电层的未保护区域完全去除的垂直轮廓刻蚀，以及第一导电层的以下各向同性蚀刻。