公开(公告)号：US20150255390A1

公开(公告)日：2015-09-10

申请号：US14721864

申请日：2015-05-26

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsin-Chieh Yao ,  Chung-Ju Lee ,  Tien-I Bao ,  Shau-Lin Shue

IPC分类号： H01L23/522 ,  H01L23/532

CPC分类号： H01L21/76897 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76808 ,  H01L21/7681 ,  H01L21/76823 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/53233 ,  H01L23/53295 ,  H01L2221/1021 ,  H01L2221/1063 ,  H01L2924/0002 ,  H01L2924/00

摘要： Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a method of manufacturing a semiconductor device includes forming an insulating material layer over a workpiece, patterning an upper portion of the insulating material layer with a conductive line pattern, and forming a stop layer comprising a metal oxide or a metal nitride over the patterned insulating material layer. A masking material is formed over the stop layer, and the masking material is patterned with a via pattern. The via pattern of the masking material is transferred to a lower portion of the insulating material layer.

摘要翻译： 公开了半导体器件及其制造方法。 在一些实施例中，制造半导体器件的方法包括在工件上形成绝缘材料层，以导电图案图案化绝缘材料层的上部，并且形成包含金属氧化物或金属氮化物的停止层 图案化的绝缘材料层。 在停止层上形成掩模材料，并且用通孔图案对掩模材料进行图案化。 掩模材料的通孔图案被转移到绝缘材料层的下部。

公开(公告)号：US20150024587A1

公开(公告)日：2015-01-22

申请号：US14277330

申请日：2014-05-14

申请人： Kyoungmi Kim ,  Myung-Sun Kim ,  Jaeho Kim ,  Hyounghee Kim ,  Namuk Choi ,  Jungsik Choi

发明人： Kyoungmi Kim ,  Myung-Sun Kim ,  Jaeho Kim ,  Hyounghee Kim ,  Namuk Choi ,  Jungsik Choi

IPC分类号： H01L21/768 ,  H01L21/027

CPC分类号： H01L21/76879 ,  H01L21/0274 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/76807 ,  H01L21/76838 ,  H01L27/11548 ,  H01L27/11575 ,  H01L2221/1021

摘要： A method of fabricating a semiconductor device is provided. An etch-target layer is formed on a substrate. A photoresist layer is formed on the etch-target layer. A first exposure process is performed using a first photo mask to form a plurality of first-irradiated patterns in the photoresist layer. The first photo mask includes a plurality of first transmission regions. Each first transmission region has different optical transmittance. A second exposure process is performed using a second photo mask to form a plurality of second-irradiated patterns in the photoresist layer. The second photo mask includes a plurality of second transmission regions. Each second transmission region has different optical transmittance. A photoresist pattern is formed from the photoresist layer by removing the plurality of first-irradiated and second-irradiated patterns from the photoresist layer. A lower structure is formed from the etch-target layer by etching the etch-target layer using the photoresist pattern.

摘要翻译： 提供一种制造半导体器件的方法。 在基板上形成蚀刻靶层。 在蚀刻靶层上形成光致抗蚀剂层。 使用第一光掩模进行第一曝光处理，以在光致抗蚀剂层中形成多个第一照射图案。 第一光掩模包括多个第一透射区域。 每个第一透射区域具有不同的透光率。 使用第二光掩模进行第二曝光处理，以在光致抗蚀剂层中形成多个第二照射图案。 第二光掩模包括多个第二透射区域。 每个第二透射区域具有不同的透光率。 通过从光致抗蚀剂层去除多个第一次照射和第二次照射的图案，从光致抗蚀剂层形成光刻胶图案。 通过使用光致抗蚀剂图案蚀刻蚀刻目标层，从蚀刻目标层形成下部结构。

公开(公告)号：US20140329379A1

公开(公告)日：2014-11-06

申请号：US14085194

申请日：2013-11-20

申请人： Samsung Electronics Co., Ltd.

发明人： Chul-Ho Kim ,  Cheolhong Kim ,  Chorong Park ,  Jaehan Lee

IPC分类号： H01L21/308 ,  H01L21/283 ,  H01L21/28

CPC分类号： H01L21/283 ,  H01L21/0274 ,  H01L21/0335 ,  H01L21/28008 ,  H01L21/31144 ,  H01L21/76807 ,  H01L21/76838 ,  H01L27/11548 ,  H01L27/11575 ,  H01L2221/1021

摘要： A patterning method includes forming a photoresist layer on a processing layer and exposing the photoresist layer using a standing wave/defocusing exposure to produce a photoresist layer having a staircase pattern.

摘要翻译： 图案化方法包括在处理层上形成光致抗蚀剂层，并使用驻波/散焦曝光曝光光致抗蚀剂层，以产生具有阶梯图案的光致抗蚀剂层。

公开(公告)号：US08652763B2

公开(公告)日：2014-02-18

申请号：US11847134

申请日：2007-08-29

申请人： Kanti Jain ,  Uttam Reddy

发明人： Kanti Jain ,  Uttam Reddy

IPC分类号： G03F7/20

CPC分类号： H05K3/107 ,  H01L21/0277 ,  H01L21/31144 ,  H01L21/76807 ,  H01L21/76813 ,  H01L2221/1021

摘要： This invention provides processing steps, methods and materials strategies for making patterns of structures for integrated electronic devices and systems. Processing methods of the present invention are capable of making micro- and nano-scale structures, such as Dual Damascene profiles, recessed features and interconnect structures, having non-uniform cross-sectional geometries useful for establishing electrical contact between device components of an electronic device. The present invention provides device fabrication methods and processing strategies using sub pixel-voting lithographic patterning of a single layer of photoresist useful for fabricating and integrating multilevel interconnect structures for high performance electronic or opto-electronic devices, particularly useful for Very Large Scale Integrated (VLSI) and Ultra large Scale Integrated (ULSI) devices. Processing methods of the present invention are complementary to conventional microfabrication and nanofabrication methods for making integrated electronics, and can be effectively integrated into existing photolithographic, etching, and thin film deposition patterning systems, processes and infrastructure.

摘要翻译： 本发明提供了用于制造集成电子设备和系统的结构图案的处理步骤，方法和材料策略。 本发明的加工方法能够制造具有非均匀横截面几何形状的微米和纳米级结构，例如双镶嵌型材，凹形特征和互连结构，其用于建立电子装置的装置部件之间的电接触 。 本发明提供了使用用于制造和集成用于高性能电子或光电子器件的多层互连结构的单层光致抗蚀剂的子像素投影光刻图案的器件制造方法和处理策略，特别适用于超大规模集成（VLSI ）和超大规模集成（ULSI）设备。 本发明的加工方法与用于制造集成电子学的常规微细加工和纳米制造方法互补，并且可以有效地集成到现有的光刻，蚀刻和薄膜沉积图案化系统，工艺和基础设施中。

公开(公告)号：US08466068B2

公开(公告)日：2013-06-18

申请号：US11967638

申请日：2007-12-31

申请人： Roy E. Scheuerlein

发明人： Roy E. Scheuerlein

IPC分类号： H01L21/311 ,  H01L21/302

CPC分类号： H01L21/48 ,  B82Y10/00 ,  B82Y40/00 ,  G03F7/0002 ,  H01L21/31144 ,  H01L21/76807 ,  H01L21/76817 ,  H01L23/5384 ,  H01L27/10 ,  H01L27/101 ,  H01L2221/1021 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides systems, apparatus, and methods for forming three dimensional memory arrays using a multi-depth imprint lithography mask and a damascene process. An imprint lithography mask for manufacturing a memory layer in a three dimensional memory is described. The mask includes a translucent material formed with features for making an imprint in a transfer material to be used in a damascene process, the mask having a plurality of imprint depths. At least one imprint depth corresponds to trenches for forming memory lines and at least one depth corresponds to holes for forming vias. Numerous other aspects are disclosed.

摘要翻译： 本发明提供使用多深度压印光刻掩模和镶嵌工艺形成三维存储器阵列的系统，装置和方法。 描述了用于制造三维存储器中的存储层的压印光刻掩模。 掩模包括半透明材料，其形成有用于在用于镶嵌工艺中的转印材料中进行印记的特征，所述掩模具有多个印痕深度。 至少一个压印深度对应于用于形成存储器线的沟槽，并且至少一个深度对应于用于形成通孔的孔。 公开了许多其他方面。

公开(公告)号：US20130026639A1

公开(公告)日：2013-01-31

申请号：US13615980

申请日：2012-09-14

申请人： John C. Arnold ,  Kuang-Jung Chen ,  Matthew E. Colburn ,  Dario L. Goldfarb ,  Stefan Harrar ,  Steven J. Holmes ,  Pushkara Varanasi

发明人： John C. Arnold ,  Kuang-Jung Chen ,  Matthew E. Colburn ,  Dario L. Goldfarb ,  Stefan Harrar ,  Steven J. Holmes ,  Pushkara Varanasi

IPC分类号： H01L21/428 ,  H01L23/48

CPC分类号： H01L23/53295 ,  G03F7/091 ,  G03F7/38 ,  H01L21/0274 ,  H01L21/31144 ,  H01L21/76811 ,  H01L21/76813 ,  H01L2221/1021 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for fabricating a dual damascene structure includes providing a first photoresist layer coated on an underlying dielectric stack, exposing said first photoresist layer to a first predetermined pattern of light, coating a second photoresist layer onto the pre-exposed first photoresist layer, exposing said second photoresist layer to a second predetermined pattern of light, optionally post-exposure baking the multi-tiered photoresist layers and developing said photoresist layers to form a multi-tiered dual damascene structure in the photoresist layers.

摘要翻译： 一种用于制造双镶嵌结构的方法包括提供涂覆在下面的电介质堆叠上的第一光致抗蚀剂层，将所述第一光致抗蚀剂层暴露于第一预定图案的光，将第二光致抗蚀剂层涂覆到预曝光的第一光致抗蚀剂层上， 第二光致抗蚀剂层到第二预定图案的光，任选地后曝光烘烤多层光致抗蚀剂层并显影所述光致抗蚀剂层以在光致抗蚀剂层中形成多层双镶嵌结构。

公开(公告)号：US08119522B1

公开(公告)日：2012-02-21

申请号：US12941184

申请日：2010-11-08

申请人： Jeffrey P. Gambino ,  Peter J. Lindgren ,  Anthony K. Stamper

发明人： Jeffrey P. Gambino ,  Peter J. Lindgren ,  Anthony K. Stamper

IPC分类号： H01L21/4763

CPC分类号： H01L21/76802 ,  H01L21/76807 ,  H01L23/5223 ,  H01L28/40 ,  H01L2221/1021 ,  H01L2221/1063

摘要： Method of forming wires in integrated circuits. The methods include forming a wire in a first dielectric layer on a substrate; forming a dielectric barrier layer over the wire and the first dielectric layer; forming a second dielectric layer over the barrier layer; forming one or more patterned photoresist layers over the second dielectric layer; performing a reactive ion etch to etch a trench through the second dielectric layer and not through the barrier layer; performing a second reactive ion etch to extend the trench through the barrier layer; and after performing the second reaction ion etch, removing the one or more patterned photoresist layers, a last formed patterned photoresist layer removed using a reducing plasma or a non-oxidizing plasma. The methods include forming wires by similar methods to a metal-insulator-metal capacitor.

公开(公告)号：US07928004B2

公开(公告)日：2011-04-19

申请号：US11671688

申请日：2007-02-06

申请人： Robert Seidel ,  Carsten Peters ,  Frank Feustel

发明人： Robert Seidel ,  Carsten Peters ,  Frank Feustel

IPC分类号： H01L21/4763

CPC分类号： B81B7/0006 ,  B81C2201/0153 ,  B82Y10/00 ,  B82Y40/00 ,  G03F7/0002 ,  H01L21/28114 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/76817 ,  H01L21/76838 ,  H01L21/76852 ,  H01L21/76885 ,  H01L2221/1021

摘要： By forming metallization structures on the basis of an imprint technique, in which via openings and trenches may be commonly formed, a significant reduction of process complexity may be achieved due to the omission of at least one further alignment process as required in conventional process techniques. Furthermore, the flexibility and efficiency of imprint lithography may be increased by providing appropriately designed imprint molds in order to provide via openings and trenches exhibiting an increased fill capability, thereby also improving the performance of the finally obtained metallization structures with respect to reliability, resistance against electromigration and the like.

摘要翻译： 通过基于压印技术形成金属化结构，其中可以通常形成通孔和沟槽，由于根据常规工艺技术所要求的至少一个进一步对准过程，可以实现工艺复杂性的显着降低。 此外，可以通过提供适当设计的压印模具来提高压印光刻的灵活性和效率，以便提供表现出增加的填充能力的通孔开口和沟槽，从而也提高了最终获得的金属化结构在可靠性，抗性 电迁移等。

公开(公告)号：US07709373B1

公开(公告)日：2010-05-04

申请号：US11553220

申请日：2006-10-26

申请人： Srikanteswara Dakshina-Murthy ,  Bhanwar Singh ,  Khoi A Phan

发明人： Srikanteswara Dakshina-Murthy ,  Bhanwar Singh ,  Khoi A Phan

IPC分类号： H01L21/4763

CPC分类号： G03F7/0002 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/76807 ,  H01L21/76817 ,  H01L2221/1021

摘要： A system and method are provided to facilitate dual damascene interconnect integration in a single imprint step. The method provides for creation of a translucent imprint mold with three-dimensional features comprising the dual damascene pattern to be imprinted. The imprint mold is brought into contact with a photopolymerizable organosilicon imaging layer deposited upon a transfer layer which is spin coated or otherwise deposited upon a dielectric layer of a substrate. When the photopolymerizable layer is exposed to a source of illumination, it cures with a structure matching the dual damascene pattern of the imprint mold. A halogen breakthrough etch followed by oxygen transfer etch transfer the vias from the imaging layer into the transfer layer. A second halogen breakthrough etch followed by a second oxygen transfer etch transfer the trenches from the imaging layer into the transfer layer. A dielectric etch transfers the pattern from the transfer layer into the dielectric layer. A metal fill process then fills the dual damascene openings of the dielectric layer with metal.

摘要翻译： 提供了一种系统和方法，以便在单个压印步骤中促进双镶嵌互连集成。 该方法提供了具有三维特征的半透明压印模具的创建，该三维特征包括要印刷的双镶嵌图案。 压印模具与沉积在转移层上的可光聚合的有机硅成像层接触，转移层被旋涂或以其它方式沉积在基底的电介质层上。 当可光聚合层暴露于照明源时，它可以用匹配印模的双镶嵌图案的结构固化。 卤素穿透蚀刻随后氧传递蚀刻将通孔从成像层转移到转移层中。 第二个卤素穿透蚀刻，随后是第二次氧转移蚀刻，将沟槽从成像层转移到转移层中。 电介质蚀刻将图案从转印层转移到电介质层中。 然后，金属填充过程用金属填充介电层的双镶嵌开口。

公开(公告)号：US20070077757A1

公开(公告)日：2007-04-05

申请号：US11320773

申请日：2005-12-30

申请人： Cheon Shim

发明人： Cheon Shim

IPC分类号： H01L21/44

CPC分类号： H01L21/76814 ,  H01L21/02063 ,  H01L21/76802 ,  H01L21/76807 ,  H01L2221/1021

摘要： A method of forming a metal wiring in a semiconductor device includes forming a lower wiring layer, forming an etch stopping film and an interlayer insulation film, forming a photo-resist pattern, forming a via-hole using the photo-resist pattern as a mask, ashing the photo-resist pattern, cleaning the via-hole, etching a portion of the etch stopping film exposed through the via-hole to expose the lower wiring layer, and burying a metallic material in the via-hole to provide a via-contact. Photo-resist residues or particles that remain after the ashing process can be perfectly removed or substantially perfectly removed through a cleaning process to open a lower metal wiring layer. It is possible to prevent the upper and lower metal wiring layers from inappropriately making contact with each other because the lower metal wiring layer is perfectly opened due to the absence of photo-resist residues.

摘要翻译： 在半导体器件中形成金属布线的方法包括形成下布线层，形成蚀刻停止膜和层间绝缘膜，形成光致抗蚀剂图案，使用光刻胶图案形成通孔 蚀刻光刻胶图案，清洁通孔，蚀刻通过通孔露出的蚀刻停止膜的一部分，露出下布线层，并将金属材料埋入通孔中， 联系。 在灰化过程之后残留的光致抗蚀剂残留物或颗粒可以通过清洁工艺被完全去除或基本上完全去除以打开下部金属布线层。 由于不存在光致抗蚀剂残留，下金属布线层完全打开，可以防止上下金属布线层彼此不适当地接触。