DATA PROCESSING METHOD, PRECODING METHOD, AND COMMUNICATION DEVICE

    公开(公告)号:US20190013895A1

    公开(公告)日:2019-01-10

    申请号:US16131261

    申请日:2018-09-14

    Abstract: An encoder outputs a first bit sequence having N bits. A mapper generates a first complex signal s1 and a second complex signal s2 with use of bit sequence having X+Y bits included in an input second bit sequence, where X indicates the number of bits used to generate the first complex signal s1, and Y indicates the number of bits used to generate the second complex signal s2. A bit length adjuster is provided after the encoder, and performs bit length adjustment on the first bit sequence such that the second bit sequence has a bit length that is a multiple of X+Y, and outputs the first bit sequence after the bit length adjustment as the second bit sequence. As a result, a problem between a codeword length of a block code and the number of bits necessary to perform mapping by a set of modulation schemes is solved.

    MODULATION METHOD AND APPARATUS
    85.
    发明申请

    公开(公告)号:US20190013824A1

    公开(公告)日:2019-01-10

    申请号:US16130293

    申请日:2018-09-13

    CPC classification number: H03M7/40 H03M13/25 H04L1/0041 H04L1/0058 H04L1/0071

    Abstract: Embodiments of this application provide a modulation method and apparatus. The method includes: receiving a code word sequence, where each code word includes N bits, and the code word sequence includes at least a first code word; mapping the code word sequence into M sequences, where each sequence includes N/M bits from the first code word; mapping the M sequences into a symbol sequence, where each symbol is corresponding to M bits, the M bits are respectively from the M sequences, first bits corresponding to N/M first-type symbols are from the first code word, and second bits corresponding to N/M second-type symbols are from the first code word. Thus a signal-to-noise ratio requirement during higher order modulation lowered.

    QC-LDPC CODES
    89.
    发明申请
    QC-LDPC CODES 审中-公开

    公开(公告)号:US20180323801A1

    公开(公告)日:2018-11-08

    申请号:US15971350

    申请日:2018-05-04

    Applicant: Mediatek Inc.

    CPC classification number: H03M13/1162 H04L1/0057 H04L1/0071

    Abstract: An apparatus determines a code block size (CBS) of information bits contained in a codeword of low-density parity check (LDPC) coding. The apparatus compares the CBS with at least one threshold, determines, based on a result of the comparison, a Kb number and determines a Kp number based on a code rate and the Kb number. The apparatus generates a parity check matrix. An information portion of the parity check matrix is a first matrix formed by M number of second square matrices. M is equal to Kp multiplied by Kb. A total number of columns in the Kb number of second square matrices is equal to a total number of bits of the CBS. One or more matrices of the M number of second square matrices are circular permutation matrices. The apparatus operates an LDPC encoder or an LDPC decoder based on the parity check matrix.

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