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公开(公告)号:US20190052511A1
公开(公告)日:2019-02-14
申请号:US16028651
申请日:2018-07-06
Applicant: NXP B.V.
Inventor: Yunus Can GULTEKIN , Frans WILLEMS , Wim VAN HOUTUM , Semih SERBETLI
CPC classification number: H04L27/366 , H03M13/256 , H03M13/27 , H03M13/6362 , H04L1/0042 , H04L1/0045 , H04L1/0059 , H04L1/0068 , H04L1/0071 , H04L27/2698 , H04L27/3405 , H04W4/44 , H04W52/0261 , H04W52/243
Abstract: An input selector for selecting an input of a convolution encoder of a transmitter is disclosed. The input selector comprises a shaper block and an input-select block. The shaper block is configured to receive an input comprising a first number of input bits, the shaper block configured to generate a shaped bit stream corresponding to the first number of input bits. The input-select block is configured to generate an encoder input bit stream for the encoder based on the shaped bit stream, wherein the input-select block generates the encoder input bit stream such that, when input into the encoder, a first bit of the encoder input bit stream sets a state of the encoder in order that a subsequent second bit of the encoder input bit stream causes the encoder to generate a bit of the shaped bit stream at a pre-determined position in an encoder output bit stream.
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公开(公告)号:US20190028121A1
公开(公告)日:2019-01-24
申请号:US16107589
申请日:2018-08-21
Applicant: LG ELECTRONICS INC.
Inventor: Hyen O OH , In Hwan CHOI , Kook Yeon KWAK , Byoung Gill KIM , Won Gyu SONG , Jin Woo KIM , Hyoung Gon LEE
IPC: H03M13/27 , H04H20/71 , H04N19/89 , H04N19/42 , H04N19/44 , H04N21/438 , H04N21/2365 , H04L1/00 , H04N21/434 , H03M13/29
CPC classification number: H03M13/2792 , H03M13/2906 , H04H20/71 , H04L1/0041 , H04L1/0071 , H04N19/42 , H04N19/44 , H04N19/89 , H04N21/2365 , H04N21/4347 , H04N21/4382
Abstract: A digital broadcasting system which is robust against an error when mobile service data is transmitted and a method of processing data are disclosed. The mobile service data is subjected to an additional coding process and the coded mobile service data is transmitted. Accordingly, it is possible to cope with a serious channel variation while applying robustness to the mobile service data.
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公开(公告)号:US20190013979A1
公开(公告)日:2019-01-10
申请号:US16125440
申请日:2018-09-07
Applicant: LG ELECTRONICS INC.
Inventor: Jongseob BAEK , Jongwoong SHIN , Jaehyung KIM , Woosuk KO , Sungryong HONG
IPC: H04L27/26 , H04L1/00 , H04L5/00 , H03M13/27 , H03M13/11 , H03M13/15 , H03M13/25 , H03M13/29 , H03M13/09
CPC classification number: H04L27/2602 , H03M13/09 , H03M13/1102 , H03M13/152 , H03M13/255 , H03M13/27 , H03M13/271 , H03M13/2742 , H03M13/2778 , H03M13/2906 , H04L1/0041 , H04L1/0045 , H04L1/0071 , H04L1/0083 , H04L5/0053 , H04L27/2605 , H04L27/2626 , H04L27/2627 , H04L27/2634 , H04L27/265 , H04L2001/0093
Abstract: A method and an apparatus for transmitting broadcast signals thereof are disclosed. The apparatus for transmitting broadcast signals comprises an encoder for encoding service data, a mapper for mapping the encoded service data into a plurality of OFDM (Orthogonal Frequency Division Multiplex) symbols to build at least one signal frame, a frequency interleaver for frequency interleaving data in the at least one signal frame by using a different interleaving-seed which is used for every OFDM symbol pair comprised of two sequential OFDM symbols, a modulator for modulating the frequency interleaved data by an OFDM scheme and a transmitter for transmitting the broadcast signals having the modulated data, wherein the different interleaving-seed is generated based on a cyclic shifting value and wherein an interleaving seed is variable based on an FFT size of the modulating.
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公开(公告)号:US20190013895A1
公开(公告)日:2019-01-10
申请号:US16131261
申请日:2018-09-14
Applicant: Sun Patent Trust
Inventor: Yutaka MURAKAMI , Tomohiro KIMURA , Mikihiro OUCHI
IPC: H04L1/00
CPC classification number: H04L1/0004 , H03M13/255 , H04B7/0413 , H04L1/0003 , H04L1/003 , H04L1/0057 , H04L1/0067 , H04L1/0071 , H04L1/08 , H04L5/005
Abstract: An encoder outputs a first bit sequence having N bits. A mapper generates a first complex signal s1 and a second complex signal s2 with use of bit sequence having X+Y bits included in an input second bit sequence, where X indicates the number of bits used to generate the first complex signal s1, and Y indicates the number of bits used to generate the second complex signal s2. A bit length adjuster is provided after the encoder, and performs bit length adjustment on the first bit sequence such that the second bit sequence has a bit length that is a multiple of X+Y, and outputs the first bit sequence after the bit length adjustment as the second bit sequence. As a result, a problem between a codeword length of a block code and the number of bits necessary to perform mapping by a set of modulation schemes is solved.
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公开(公告)号:US20190013824A1
公开(公告)日:2019-01-10
申请号:US16130293
申请日:2018-09-13
Applicant: Huawei Technologies Co., Ltd.
Inventor: Xi YAN , Huixiao MA , Wai Kong Raymond LEUNG , Long LUO , Yan CUI
CPC classification number: H03M7/40 , H03M13/25 , H04L1/0041 , H04L1/0058 , H04L1/0071
Abstract: Embodiments of this application provide a modulation method and apparatus. The method includes: receiving a code word sequence, where each code word includes N bits, and the code word sequence includes at least a first code word; mapping the code word sequence into M sequences, where each sequence includes N/M bits from the first code word; mapping the M sequences into a symbol sequence, where each symbol is corresponding to M bits, the M bits are respectively from the M sequences, first bits corresponding to N/M first-type symbols are from the first code word, and second bits corresponding to N/M second-type symbols are from the first code word. Thus a signal-to-noise ratio requirement during higher order modulation lowered.
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公开(公告)号:US20180373589A1
公开(公告)日:2018-12-27
申请号:US15842692
申请日:2017-12-14
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor: John K. DeBrosse , Daniel C. Worledge
CPC classification number: G06F11/1016 , G11C11/16 , G11C29/06 , G11C29/34 , G11C29/42 , G11C29/4401 , G11C29/52 , G11C29/789 , G11C2029/0403 , G11C2029/4402 , H01L27/222 , H01L43/08 , H03M13/2764 , H04L1/0071
Abstract: A memory device, a memory system, and corresponding methods are provided. The memory device includes a non-volatile random access memory. The non-volatile memory includes a suspect bit register configured to store addresses of bits that are determined to have had errors. The non-volatile memory further includes a bad bit register configured to store addresses of bits that both (i) appeared in the suspect bit register due to a first error and (ii) are determined to have had a second error. Hence, the memory device overcomes the aforementioned intrinsic write-error-rate by identifying the bad bits so they can be fused out, thus avoiding errors during use of the non-volatile random access memory.
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公开(公告)号:US20180343021A1
公开(公告)日:2018-11-29
申请号:US15993269
申请日:2018-05-30
Applicant: SATURN LICENSING LLC
Inventor: Ryoji IKEGAYA , Makiko Yamamoto , Yuji Shinohara
CPC classification number: H03M13/616 , H03M13/1111 , H03M13/116 , H03M13/1165 , H03M13/1177 , H03M13/1185 , H03M13/152 , H03M13/253 , H03M13/255 , H03M13/2778 , H03M13/2792 , H03M13/2906 , H04L1/0057 , H04L1/0071 , H04L2001/0093
Abstract: The present technology relates to a data processing device and a data processing method which can ensure high communication quality in data transmission using LDPC codes.In group-wise interleaving, an LDPC code having a code length N of 64800 bits and a coding rate r of 11/15 is interleaved in a unit of a bit group of 360 bits. In group-wise deinterleaving, a sequence of bit groups of the LDPC code which has been subjected to the group-wise interleaving is returned to an original sequence. The present technology can be applied to, for example, a case in which data transmission is performed using LDPC codes.
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公开(公告)号:US20180331786A1
公开(公告)日:2018-11-15
申请号:US16045002
申请日:2018-07-25
Applicant: Apple Inc.
Inventor: Robert Novak , Hosein Nikopourdeilami , Mo-Han Fong , Sophie Vrzic
CPC classification number: H04L1/0668 , H04B7/0473 , H04B7/0667 , H04L1/0003 , H04L1/0009 , H04L1/0026 , H04L1/0067 , H04L1/0071 , H04L1/0643 , H04L1/1812 , H04L1/1816 , H04L1/1893 , H04L5/0026 , H04L27/2628
Abstract: A method for transmitting data in a multiple-input-multiple-output space-time coded communication using a mapping table mapping a plurality of symbols defining the communication to respective antennae from amongst a plurality of transmission antennae and to at least one other transmission resource. The mapping table may comprise Alamouti-coded primary segments and may also comprise secondary segments, comprising primary segments. The primary segments in the secondary segments may be defined in accordance to an Alamouti based code pattern applied at the segment level to define a segment-level Alamouti based code.
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公开(公告)号:US20180323801A1
公开(公告)日:2018-11-08
申请号:US15971350
申请日:2018-05-04
Applicant: Mediatek Inc.
Inventor: Cheng-Yi HSU , Chong-You LEE , Wei Jen CHEN , Maoching CHIU , Timothy Perrin FISHER-JEFFES , Ju-Ya CHEN , Yen Shuo CHANG
CPC classification number: H03M13/1162 , H04L1/0057 , H04L1/0071
Abstract: An apparatus determines a code block size (CBS) of information bits contained in a codeword of low-density parity check (LDPC) coding. The apparatus compares the CBS with at least one threshold, determines, based on a result of the comparison, a Kb number and determines a Kp number based on a code rate and the Kb number. The apparatus generates a parity check matrix. An information portion of the parity check matrix is a first matrix formed by M number of second square matrices. M is equal to Kp multiplied by Kb. A total number of columns in the Kb number of second square matrices is equal to a total number of bits of the CBS. One or more matrices of the M number of second square matrices are circular permutation matrices. The apparatus operates an LDPC encoder or an LDPC decoder based on the parity check matrix.
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公开(公告)号:US20180287842A1
公开(公告)日:2018-10-04
申请号:US15882156
申请日:2018-01-29
Applicant: Intel Corporation
Inventor: Bernard Arambepola , Parveen K. Shukla , Thushara Hewavithana , Sahan S. Gamage
CPC classification number: H04L27/2627 , G06F7/768 , G06F12/00 , H03M13/271 , H04L1/0071 , H04L27/2628 , H04L27/263 , H04L27/2634 , H05K999/99
Abstract: The disclosure generally relates to a method and apparatus for frequency interleaving. Specifically, an embodiment of the disclosure relates to a communication system having one or more antennas, a radio, a memory circuit, and a processor circuit. The antennas can be used to communicate signals or to comply with different transmission protocols. The radio can be configured to send and receive radio signals. The memory can communicate with the processor circuit and contain instructions for the processor circuit to write data carriers along a plurality of rows and columns of a 2-D store in bit-reversed order and read the columns of 2-D store.
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