公开(公告)号：US20240296895A1

公开(公告)日：2024-09-05

申请号：US18662238

申请日：2024-05-13

Applicant: Kioxia Corporation

Inventor： Noboru SHIBATA ,  Hironori UCHIKAWA ,  Taira SHIBUYA

IPC: G11C16/26 ,  G06F3/06 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/32 ,  G11C16/34 ,  H10B69/00

CPC classification number: G11C16/26 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0679 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/32 ,  G11C16/3459 ,  H10B69/00

Abstract: A semiconductor memory includes a first memory cell configured to be set with a first threshold voltage, the first threshold voltage being one of different threshold voltage levels, a second memory cell configured to be set with a second threshold voltage, the second threshold voltage being one of different threshold voltage levels, a first word line coupled to the first memory cell, a second word line coupled to the second memory cell, and a controller configured to read data of one of different bits based on a combination of the first threshold voltage of the first memory cell and the second threshold voltage of the second memory cell.

公开(公告)号：US12082408B2

公开(公告)日：2024-09-03

申请号：US17481803

申请日：2021-09-22

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Yuancheng Yang ,  Wenxi Zhou ,  Zhiliang Xia ,  Wei Liu

IPC: H10B41/41 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  H01L23/528 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

CPC classification number: H10B41/41 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  H01L23/5283 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first and second semiconductor structures. The first semiconductor structure includes an array of NAND memory strings, a first peripheral circuit of the array of NAND memory strings including a first transistor, a polysilicon layer between the array of NAND memory strings and the first peripheral circuit, and a first semiconductor layer in contact with the first transistor. The polysilicon layer is in contact with sources of the array of NAND memory strings. The second semiconductor structure includes a second peripheral circuit of the array of NAND memory strings including a second transistor, and a second semiconductor layer in contact with the second transistor. The second peripheral circuit is between the bonding interface and the second semiconductor layer. The first semiconductor layer is between the polysilicon layer and the second semiconductor layer.

公开(公告)号：US12073898B2

公开(公告)日：2024-08-27

申请号：US18361132

申请日：2023-07-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eun-Ji Kim ,  Jung-June Park ,  Jeong-Don Ihm ,  Byung-Hoon Jeong ,  Young-Don Choi

IPC: G11C5/06 ,  G11C7/10 ,  G11C16/06 ,  G11C16/10 ,  G11C16/26 ,  G11C29/02

CPC classification number: G11C29/025 ,  G11C5/063 ,  G11C7/1048 ,  G11C7/1057 ,  G11C7/1084 ,  G11C16/06 ,  G11C16/102 ,  G11C16/26 ,  G11C29/022 ,  G11C29/028

Abstract: A nonvolatile memory (NVM) device includes a data pin, a control pin, an on-die termination (ODT) pin, and a plurality of NVM memory chips commonly connected to the data pin and the control pin. A first NVM chip among the NVM chips includes an ODT circuit. The first NVM chip determines one of an ODT write mode and an ODT read mode based on a control signal received through the control pin and an ODT signal received through the ODT pin, uses the ODT circuit to perform an ODT on the data pin during the ODT write mode, and uses the ODT circuit to perform the ODT on the control pin during the ODT read mode.

公开(公告)号：US12073891B2

公开(公告)日：2024-08-27

申请号：US17682089

申请日：2022-02-28

Applicant: Micron Technology, Inc.

Inventor： Eric N. Lee ,  Violante Moschiano ,  Jeffrey S. McNeil ,  James Fitzpatrick ,  Sivagnanam Parthasarathy ,  Kishore Kumar Muchherla ,  Patrick R. Khayat

IPC: G11C16/30 ,  G11C16/10 ,  G11C16/26

CPC classification number: G11C16/30 ,  G11C16/102 ,  G11C16/26 ,  G11C2207/2254

Abstract: Processing logic in a memory device receives a command to execute a set of read operations having read voltage levels corresponding to a programming distribution associated with the memory device. A set of memory bit counts is determined, where each memory bit count corresponds to a respective bin of a set of bins associated with the multiple read voltage levels of the set of read operations. A valley center bin having a minimum memory bit count of the set of memory bit counts is determined. The processing logic determines that the minimum memory bit count of the valley center bin satisfies a condition and an adjusted read voltage level associated with the valley center bin is identified in response to the condition being satisfied.

公开(公告)号：US20240284668A1

公开(公告)日：2024-08-22

申请号：US18653241

申请日：2024-05-02

Applicant: KIOXIA CORPORATION

Inventor： Takehiko AMAKI ,  Yoshihisa KOJIMA ,  Toshikatsu HIDA ,  Marie Grace Izabelle Angeles SIA ,  Riki SUZUKI ,  Shohei ASAMI

IPC: H10B41/27 ,  G11C7/04 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  H10B43/27 ,  H10B43/35

CPC classification number: H10B41/27 ,  G11C7/04 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/107 ,  G11C16/16 ,  G11C16/26 ,  H10B43/27 ,  H10B43/35

Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes blocks each containing memory cells. The controller is configured to instruct the semiconductor memory to execute a first operation and a second operation. In the first operation and the second operation, the semiconductor memory selects at least one of the blocks, and applies at least one voltage to all memory cells contained in said selected blocks. A number of blocks to which said voltage is applied per unit time in the second operation is larger than that in the first operation.

公开(公告)号：US20240282392A1

公开(公告)日：2024-08-22

申请号：US18346332

申请日：2023-07-03

Applicant: SanDisk Technologies LLC

Inventor： Hua-Ling Cynthia Hsu ,  Frank Wanfang Tsai

IPC: G11C16/34 ,  G11C7/10 ,  G11C16/10 ,  G11C16/26

CPC classification number: G11C16/3459 ,  G11C7/1039 ,  G11C16/102 ,  G11C16/26

Abstract: An apparatus includes a control circuit that is configured to connect to an array of non-volatile memory cells. The control circuit includes a first plurality of data latches configured to connect to non-volatile memory cells of a first plane and a second plurality of data latches configured to connect to non-volatile memory cells of a second plane. The control circuit also includes a shared data transfer data latch configured for transfer of data with the first plurality of data latches and the second plurality of data latches. The shared transfer data latch can be used to transfer data for operations being performed on a first plane to use the data latches on the other plane for storing data for operations on the first plane.

公开(公告)号：US20240282380A1

公开(公告)日：2024-08-22

申请号：US18311248

申请日：2023-05-03

Applicant: Winbond Electronics Corp.

Inventor： Yi-Chen Fan ,  Chieh-Yen Wang

IPC: G11C16/10 ,  G11C16/16 ,  G11C16/24 ,  G11C16/34

CPC classification number: G11C16/102 ,  G11C16/16 ,  G11C16/24 ,  G11C16/3459

Abstract: An operation method for a memory device is provided. A memory block of the memory device includes an array of memory cells including cell strings and cell pages. Serially numbered and arranged bit lines are connected to the cell strings, respectively. Serially numbered and arranged word lines are connected to the cell pages, respectively. The operation method includes: performing a batch writing to each of the cell pages, such that the memory cells in each cell page are respectively grouped as an earlier written memory cell or a later written memory cell, depending on the connected bit line is either even-numbered or odd-numbered. Each cell page has a respective write sequence. In terms of write sequence, each cell page is identical with one of 2 nearest cell pages, and opposite to the other of the 2 nearest cell pages.

公开(公告)号：US12068046B2

公开(公告)日：2024-08-20

申请号：US17828262

申请日：2022-05-31

Applicant: SK hynix Inc.

Inventor： Jang Seob Kim ,  Sang Ho Yun

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26

CPC classification number: G11C16/3459 ,  G11C16/102 ,  G11C16/26 ,  G11C16/3404

Abstract: A storage device includes: a memory device including a plurality of memory cells, the memory device performing a read operation of reading data stored in selected memory cells among the plurality of memory cells; and a memory controller for receiving a read request from a host, and controlling the memory device to perform the read operation corresponding to the read request. The memory controller includes a read voltage inferrer for, when the read operation is completed, receiving read information on the read operation from the memory device, performing a read quality evaluation operation of evaluating the read operation based on the read information, and performing a read voltage inference operation of inferring a secondary read level corresponding to the read information according to a result of the performing the read quality evaluation operation.

公开(公告)号：US12068035B2

公开(公告)日：2024-08-20

申请号：US17944658

申请日：2022-09-14

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Zhipeng Dong

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24

CPC classification number: G11C16/102 ,  G11C16/0433 ,  G11C16/08 ,  G11C16/24

Abstract: A memory, a programming method, and a memory system are provided. The programming method includes programming a selected memory cell string according to a programming sequence; applying, when programming a memory cell in the selected memory cell string that is coupled to a selected non-edge word line in a plurality of word lines, a first pass voltage to edge word lines in the plurality of word lines; and applying a second pass voltage to a non-edge word line adjacent to the edge word lines. The edge word lines are at least one word line in the plurality of word lines adjacent to the source line or to the bit line; the non-edge word lines are word lines in the plurality of word lines other than the edge word lines; and the selected non-edge word line is not adjacent to the edge word lines.

公开(公告)号：US12062402B2

公开(公告)日：2024-08-13

申请号：US17385493

申请日：2021-07-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byungsoo Kim ,  Hyunggon Kim ,  Kyungsoo Park ,  Sejin Baek ,  Sangbum Yun

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/30 ,  G11C16/34

CPC classification number: G11C16/3459 ,  G11C16/0433 ,  G11C16/08 ,  G11C16/102 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30

Abstract: A non-volatile memory device including a memory cell array including a plurality of cell strings, wherein each cell string of the plurality of cell stings includes a string selection transistor, a plurality of memory cells, and a ground selection transistor connected in series between a bit line and a common source line; and a control circuit configured to perform a program operation on a selected memory cell from among the plurality of memory cells and pre-charge a selected cell string including the selected memory cell in a pre-charge section included in a verification section, wherein the selected cell string is pre-charged as a first pre-charge voltage is applied to a selected bit line connected to the selected memory cell.