公开(公告)号：US11848240B2

公开(公告)日：2023-12-19

申请号：US17114082

申请日：2020-12-07

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shu-Uei Jang ,  Chen-Huang Huang ,  Ryan Chia-Jen Chen ,  Shiang-Bau Wang ,  Shu-Yuan Ku

IPC分类号： H01L21/8234 ,  H01L29/66 ,  H01L21/033 ,  H01L21/308 ,  H01L21/762 ,  H01L27/088 ,  H01L29/78

CPC分类号： H01L21/823431 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/76224 ,  H01L21/823437 ,  H01L21/823468 ,  H01L27/0886 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

摘要： A conductive gate over a semiconductor fin is cut into a first conductive gate and a second conductive gate. An oxide is removed from sidewalls of the first conductive gate and a dielectric material is applied to the sidewalls. Spacers adjacent to the conductive gate are removed to form voids, and the voids are capped with a dielectric material to form air spacers.

公开(公告)号：US20230402287A1

公开(公告)日：2023-12-14

申请号：US17836452

申请日：2022-06-09

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Kuan-Da HUANG ,  Chun-Fu KUO ,  Yi-Hsing YU ,  Li-Te LIN

IPC分类号： H01L21/308 ,  H01L21/3065 ,  H01L21/02 ,  H01L29/66

CPC分类号： H01L21/3083 ,  H01L21/3065 ,  H01L21/02057 ,  H01L29/66545 ,  H01L29/42392

摘要： A method for manufacturing a semiconductor structure includes forming a semiconductor portion which has an exposed region; forming two fin sidewalls which are disposed at two opposite sides of the exposed region of the semiconductor portion, and which include a dielectric material; and performing an etching process such that the exposed region of the semiconductor portion is etched away to form a recess while a protection layer is formed to protect each of the fin sidewalls during the etching process. Other methods for manufacturing the semiconductor structure are also disclosed.

公开(公告)号：US11842932B2

公开(公告)日：2023-12-12

申请号：US17739899

申请日：2022-05-09

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chang-Yin Chen ,  Che-Cheng Chang ,  Chih-Han Lin

IPC分类号： H01L29/49 ,  H01L29/423 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/51 ,  H01L21/308 ,  H01L27/092 ,  H01L29/10 ,  H01L21/306 ,  H01L21/3065

CPC分类号： H01L21/82385 ,  H01L21/3065 ,  H01L21/3086 ,  H01L21/30608 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/1033 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66795

摘要： A method includes providing a substrate having a channel region, forming a gate stack layer over the channel region, forming a patterned hard mask over the gate stack layer, etching a top portion of the gate stack layer through openings in the patterned hard mask with a first etchant, etching a middle portion and a bottom portion of the gate stack layer with a second etchant that includes a passivating gas. A gate stack is formed with a passivation layer deposited on sidewalls of the gate stack. The method also includes etching the gate stack with a third etchant, thereby removing a bottom portion of the passivation layer and recessing a bottom portion of the gate stack.

公开(公告)号：US20230386840A1

公开(公告)日：2023-11-30

申请号：US18232737

申请日：2023-08-10

申请人： TAIWAN SEMICONDUCTOR MANUFACTRING COMPANY, LTD.

发明人： An-Ren ZI ,  Chun-Chih HO ,  Yahru CHENG ,  Ching-Yu CHANG

IPC分类号： H01L21/033 ,  G03F7/00 ,  H01L21/308

CPC分类号： H01L21/0334 ,  G03F7/70033 ,  H01L21/3083

摘要： In a method of manufacturing a semiconductor device, a metallic photoresist layer is formed over a target layer to be patterned, the metallic photoresist layer is selectively exposed to actinic radiation to form a latent pattern, and the latent pattern is developed by applying a developer to the selectively exposed photoresist layer to form a pattern. The metallic photo resist layer is an alloy layer of two or more metal elements, and the selective exposure changes a phase of the alloy layer.

公开(公告)号：US20230386826A1

公开(公告)日：2023-11-30

申请号：US18358508

申请日：2023-07-25

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Wei-Che Hsieh ,  Ching Yu Huang ,  Hsin-Hao Yeh ,  Chunyao Wang ,  Tze-Liang Lee

IPC分类号： H01L21/02 ,  H01L21/762 ,  H01L21/033 ,  H01L21/308 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/78

CPC分类号： H01L21/0217 ,  H01L21/76224 ,  H01L21/0337 ,  H01L21/02208 ,  H01L21/3086 ,  H01L21/0228 ,  H01L29/66795 ,  H01L21/3081 ,  H01L29/66545 ,  H01L21/823431 ,  H01L29/785

摘要： A method includes placing a wafer into a process chamber, and depositing a silicon nitride layer on a base layer of the wafer. The process of depositing the silicon nitride layer includes introducing a silicon-containing precursor into the process chamber, purging the silicon-containing precursor from the process chamber, introducing hydrogen radicals into the process chamber, purging the hydrogen radicals from the process chamber; introducing a nitrogen-containing precursor into the process chamber, and purging the nitrogen-containing precursor from the process chamber.

公开(公告)号：US11830727B2

公开(公告)日：2023-11-28

申请号：US17809917

申请日：2022-06-30

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Wei-Che Hsieh ,  Ching Yu Huang ,  Hsin-Hao Yeh ,  Chunyao Wang ,  Tze-Liang Lee

IPC分类号： H01L21/02 ,  H01L29/66 ,  H01L29/78 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/033 ,  H01L21/308

CPC分类号： H01L21/0217 ,  H01L21/0228 ,  H01L21/02208 ,  H01L21/0337 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/76224 ,  H01L21/823431 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

摘要： A method includes placing a wafer into a process chamber, and depositing a silicon nitride layer on a base layer of the wafer. The process of depositing the silicon nitride layer includes introducing a silicon-containing precursor into the process chamber, purging the silicon-containing precursor from the process chamber, introducing hydrogen radicals into the process chamber, purging the hydrogen radicals from the process chamber; introducing a nitrogen-containing precursor into the process chamber, and purging the nitrogen-containing precursor from the process chamber.

公开(公告)号：US11824058B2

公开(公告)日：2023-11-21

申请号：US18082333

申请日：2022-12-15

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Kuo-Cheng Ching ,  Shi Ning Ju ,  Ching-Wei Tsai ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC分类号： H01L27/092 ,  H01L21/308 ,  H01L21/8238 ,  H01L21/28 ,  H01L29/66 ,  H01L29/78 ,  H01L29/49 ,  H01L29/51

CPC分类号： H01L27/0924 ,  H01L21/28088 ,  H01L21/3086 ,  H01L21/823821 ,  H01L21/823864 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/785

摘要： Aspects of the disclosure provide a semiconductor device and a method for forming the semiconductor device. The method for forming a semiconductor device includes forming a first stack of channel structures that extends between a source terminal and a drain terminal of a first transistor in a first region of the semiconductor device. The first stack of channel structures includes a first channel structure and a second channel structure. The method further includes forming a first gate structure that wraps around the first stack of channel structures with a first metal cap between the first channel structure and the second channel structure. The first metal cap has a different work function from another portion of the first gate structure.

公开(公告)号：US11824022B2

公开(公告)日：2023-11-21

申请号：US17590411

申请日：2022-02-01

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Tzu-Hsuan Yeh ,  Chern-Yow Hsu

IPC分类号： H01L23/00 ,  H01L21/308

CPC分类号： H01L24/03 ,  H01L21/308 ,  H01L24/05 ,  H01L2224/03831

摘要： The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a bond pad disposed over a substrate and a passivation structure disposed over the substrate and the bond pad. The passivation structure has one or more sidewalls directly over the bond pad. A protective layer is disposed directly between the passivation structure and the bond pad. The passivation structure extends from directly over the protective layer to laterally past a sidewall of the protective layer that faces a central region of the bond pad.

公开(公告)号：US20230369048A1

公开(公告)日：2023-11-16

申请号：US18227231

申请日：2023-07-27

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Jia-Lin WEI ,  Ming-Hui Weng ,  Chih-Cheng Liu ,  Yi-Chen Kuo ,  Yen-Yu Chen ,  Yahru Cheng ,  Jr-Hung Li ,  Ching-Yu Chang ,  Tze-Liang Lee ,  Chi-Ming Yang

IPC分类号： H01L21/033 ,  H01L21/308 ,  G03F7/00 ,  G03F1/22

CPC分类号： H01L21/0332 ,  H01L21/3081 ,  G03F7/70033 ,  G03F1/22 ,  H01L21/0334

摘要： A method of manufacturing semiconductor device includes forming a multilayer photoresist structure including a metal-containing photoresist over a substrate. The multilayer photoresist structure includes two or more metal-containing photoresist layers having different physical parameters. The metal-containing photoresist is a reaction product of a first precursor and a second precursor, and each layer of the multilayer photoresist structure is formed using different photoresist layer formation parameters. The different photoresist layer formation parameters are one or more selected from the group consisting of the first precursor, an amount of the first precursor, the second precursor, an amount of the second precursor, a length of time each photoresist layer formation operation, and heating conditions of the photoresist layers. The multilayer photoresist structure is selectively exposed to actinic radiation to form a latent pattern, and the latent pattern is developed by applying developer to the selectively exposed multilayer photoresist structure to form the pattern.

公开(公告)号：US11817312B2

公开(公告)日：2023-11-14

申请号：US16173988

申请日：2018-10-29

申请人： APPLIED MATERIALS, INC.

发明人： Akhil Mehrotra ,  Vinay Shankar Vidyarthi ,  Daksh Agarwal ,  Samaneh Sadighi ,  Jason Kenney ,  Rajinder Dhindsa

IPC分类号： H01L21/02 ,  H01L21/3065 ,  H01J37/32 ,  H01L21/67 ,  H01L21/66 ,  H01L21/308

CPC分类号： H01L21/02274 ,  H01J37/32146 ,  H01L21/0228 ,  H01L21/308 ,  H01L21/3065 ,  H01L21/67069 ,  H01L22/26

摘要： A method, apparatus and system for processing a wafer in a plasma chamber system, which includes at least a plasma generating element and a biasing electrode, include generating a plasma in the plasma chamber system by applying a source RF source power to the plasma generating element for a first period of time of a pulse period of the RF source power, after the expiration of the first period of time, removing the source RF source power, after a delay after the removal of the RF source power, applying an RF bias signal to the biasing electrode for a second period of time to bias the generated plasma towards the wafer, and after the expiration of the second period of time, removing the RF bias signal from the biasing electrode before a next pulse period of the RF source power. The generated plasma biased toward the wafer is used to process the wafer.