公开(公告)号：US5237485A

公开(公告)日：1993-08-17

申请号：US602926

申请日：1990-10-22

申请人： Carlo Cognetti de Martiis ,  Bruno Murari

发明人： Carlo Cognetti de Martiis ,  Bruno Murari

IPC分类号： H01L23/40 ,  H05K1/02

CPC分类号： H01L23/4006 ,  H01L23/4093 ,  H05K1/0203 ,  H01L2023/405 ,  H01L2023/4062 ,  H01L2023/4087 ,  H01L2924/0002 ,  H05K2201/10166 ,  H05K2201/10386 ,  H05K2201/10393 ,  H05K2201/10409 ,  H05K2201/10446 ,  H05K3/0061

摘要： A heat sink and method for heat sinking a package containing electronic components is described. The heat sinking is accomplished by use of a cooling plate located beneath a circuit board. The package having leads extending from more than one side of the package is positioned on the cooling plate so that the leads from the sides of the package can be electrically coupled to conductors on the circuit board wherein the circuit board is disposed about at least two and preferably three sides of the package. The package is secured to the cooling plate by a spring clip. The spring clip permits flexible positioning of the package relative to the cooling plate including positioning the package in close proximity of the edge of the cooling plate. Thermal conduction between the package and the cooling plate can be enhanced by the presence of a compressible thermally-conducting material. The circuit board preferably has an opening therein so as to permit the board to be in close proximity to the three sides of the package for increased connectibility.

摘要翻译： 描述了一种用于散热包含电子部件的包装的散热器和方法。 通过使用位于电路板下方的冷却板来实现散热。 具有从封装的多于一侧延伸的引线的封装被定位在冷却板上，使得来自封装侧面的引线可以电耦合到电路板上的导体，其中电路板被设置在至少两个和 最好是包装的三面。 包装通过弹簧夹固定到冷却板。 弹簧夹允许包装相对于冷却板的灵活定位，包括将包装定位在冷却板的边缘附近。 可以通过存在可压缩的导热材料来增强封装和冷却板之间的热传导。 电路板优选地具有开口，以允许电路板靠近封装的三个侧面，以增加可连接性。

公开(公告)号：US4892836A

公开(公告)日：1990-01-09

申请号：US028842

申请日：1987-03-23

申请人： Antonio Andreini ,  Claudio Contiero ,  Paola Galbiati

发明人： Antonio Andreini ,  Claudio Contiero ,  Paola Galbiati

IPC分类号： H01L21/033 ,  H01L21/76 ,  H01L21/8234 ,  H01L21/8236 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/088 ,  H01L27/092 ,  H01L29/78

CPC分类号： H01L21/8236 ,  H01L21/033 ,  H01L21/823456 ,  H01L27/0922

摘要： This method, requiring a reduced number of process phases and providing an efficient, high-voltage structure, comprises forming a P-well region of the N-channel transistor of a CMOS device, by means of boron atom implant through a protective mask, forming at least one insulation region surrounding the CMOS device, forming edge regions having the same conductivity type as the insulation region but with a smaller concentration of impurities on at least one part of the insulation region and in the high-voltage electronic devices by means of the same boron atom implant used to form the P-well region.

摘要翻译： 该方法需要减少数量的工艺阶段并提供有效的高电压结构，包括通过硼原子注入通过保护掩模形成CMOS器件的N沟道晶体管的P阱区域，形成 围绕所述CMOS器件的至少一个绝缘区域，形成具有与所述绝缘区域相同的导电类型但在所述绝缘区域的至少一部分上以及所述高压电子器件中的较小的杂质浓度的边缘区域，借助于所述绝缘区域 用于形成P阱区的相同的硼原子注入。

公开(公告)号：US4888307A

公开(公告)日：1989-12-19

申请号：US90142

申请日：1987-08-27

申请人： Antonio P. Spairisano ,  Marino Cellai

发明人： Antonio P. Spairisano ,  Marino Cellai

IPC分类号： B29C33/12 ,  B29C45/14 ,  B29C70/72 ,  H01L21/56 ,  H01L23/31

CPC分类号： H01L23/3107 ,  B29C33/123 ,  B29C45/14065 ,  B29C45/14073 ,  B29C70/72 ,  H01L21/565 ,  H01L24/97 ,  B29C2045/14122 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/12033 ,  H01L2924/1815 ,  Y10T29/49158 ,  Y10T29/49172

摘要： A method for correctly positioning a metallic plate supporting a semiconductor chip in a mold used for encapsulation, wherein according to a first solution, at least a pair of retractable locating pins are utilized together with a lead connected to the supporting plate. The ends of the locating pins are retracted in the final phase of encapsulation, from the surfaces of the plate, whereas in the initial phase they are in direct contact with the surfaces. According to a second solution, a pair of clamping pins are indirectly connected to the plate through the interposition of insulating thicknessings.

摘要翻译： 一种用于将支撑半导体芯片的金属板正确定位在用于封装的模具中的方法，其中根据第一解决方案，至少一对可缩回的定位销与连接到支撑板的引线一起使用。 定位销的端部在封装的最后阶段从板的表面缩回，而在初始阶段，它们与表面直接接触。 根据第二种解决方案，一对夹紧销通过插入绝缘厚度间接连接到板。

公开(公告)号：US4887142A

公开(公告)日：1989-12-12

申请号：US276890

申请日：1988-11-28

申请人： Franco Bertotti ,  Carlo Cini ,  Claudio Contiero ,  Paola Galbiati

发明人： Franco Bertotti ,  Carlo Cini ,  Claudio Contiero ,  Paola Galbiati

IPC分类号： H01L21/8249 ,  H01L27/06

CPC分类号： H01L21/8249 ,  H01L27/0623

摘要： Disclosed is a monolithic integrated semiconductor device which may contain specimens of seven different circuit components; namely: lateral N-MOS and lateral P-MOS transistors (CMOS), vertical N-DMOS and vertical P-DMOS transistors, vertical NPN bipolar transistors, vertical PNP bipolar transistors with isolated collector and low leakage junction diodes as well as a process for fabricating such a device.

摘要翻译： 公开了一种单片集成半导体器件，其可以包含七个不同电路部件的样本; 即：横向N-MOS和横向P-MOS晶体管（CMOS），垂直N-DMOS和垂直P-DMOS晶体管，垂直NPN双极晶体管，具有隔离集电极和低漏极结二极管的垂直PNP双极晶体管以及用于 制造这样的装置。

公开(公告)号：US4871963A

公开(公告)日：1989-10-03

申请号：US258962

申请日：1988-10-17

申请人： Lucio Cozzi

发明人： Lucio Cozzi

IPC分类号： H01L27/10 ,  G01R31/26 ,  G01R31/28 ,  G01R31/30 ,  G11C29/00 ,  G11C29/06 ,  G11C29/50 ,  H01L21/66 ,  H01L21/8247 ,  H01L29/788 ,  H01L29/792

CPC分类号： G01R31/2868 ,  G01R31/2642 ,  G11C29/50 ,  G11C29/50012 ,  G11C29/50016 ,  G11C16/04

摘要： An apparatus and a relative method which permit carrying out a complete cycle of functional tests and parametric measurements on EPROM type semiconductor devices during their permanence inside a burn-in chamber, thus greatly reducing the time necessary for testing and classifying the devices, besides ensuring a higher reliability. The system utilizes special "intelligent" cards, i.e., provided with a card microprocessor which may be connected to a supervisory system's CPU directing the test and classification process of the devices.

公开(公告)号：US4837464A

公开(公告)日：1989-06-06

申请号：US55954

申请日：1987-06-01

申请人： Roberto Viscardi ,  Silvano Gornati ,  Silvano Coccetti

发明人： Roberto Viscardi ,  Silvano Gornati ,  Silvano Coccetti

IPC分类号： H03K5/26 ,  G09G5/12 ,  G09G5/18 ,  H03K4/90 ,  H03K5/13 ,  H03L7/06

CPC分类号： G09G5/12

摘要： This circuit comprises a phase-lock stage receiving at the input a reference signal and the synchronism signal EN and generating at the output a triangular signal in phase correlation with the synchronism signal, a rectangular waveform generator receiving at the input the triangular signal and supplying at the output a rectangular signal, a drive element receiving the rectangular signal and generating a periodic control signal, as well as a phase comparator receiving at the input the triangular signal and the control signal, as well as a further reference signal and generating at the output an error signal correlated with the phase shift of the drive element and fed to the rectangular waveform generator. The reference signal fed to the phase-lock stage or to the phase comparator can be suitably varied within preset limits by an external potentiometer.

摘要翻译： 该电路包括相位锁定级，在输入端接收参考信号和同步信号EN，并在输出端产生与同步信号相位相关的三角形信号;矩形波形发生器，在输入端接收三角形信号并在 输出矩形信号，接收矩形信号并产生周期性控制信号的驱动元件以及在输入端接收三角波信号和控制信号的相位比较器以及另一参考信号并在输出端产生 与驱动元件的相移相关并馈送到矩形波形发生器的误差信号。 馈送到锁相级或相位比较器的参考信号可以通过外部电位器在预设的限制内适当变化。

公开(公告)号：US4823316A

公开(公告)日：1989-04-18

申请号：US119498

申请日：1987-11-12

申请人： Carlo Riva

发明人： Carlo Riva

IPC分类号： H01L21/8247 ,  H01L29/788 ,  H01L29/792 ,  G11C13/00 ,  G11C11/40

CPC分类号： H01L29/7883

摘要： The memory cell comprises a selection transistor, pickup transistor and a tunnel condenser formed using a single layer of polysilicon. The tunnel condenser is formed on an active area distinct and separate from that of the pickup transistor.

摘要翻译： 存储单元包括选择晶体管，拾取晶体管和使用单层多晶硅形成的隧道电容器。 隧道冷凝器形成在与拾取晶体管不同且分离的有源区域上。

公开(公告)号：US4816883A

公开(公告)日：1989-03-28

申请号：US64480

申请日：1987-06-22

申请人： Livio Baldi

发明人： Livio Baldi

IPC分类号： H01L21/8247 ,  H01L21/8246 ,  H01L27/112 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L29/78 ,  G11C11/34 ,  H01L27/02

CPC分类号： H01L29/7885 ,  H01L27/115

摘要： A nonvolatile, EPROM type memory cell, formed using a p-channel MOS device instead of an n-channel MOS device as customary according to the prior art, offers several advantages: improved programming characteristics, a relatively low gate voltage for writing, a lower power dissipation and above all compatability with the great majority of CMOS fabrication processes. An explanation of such surprising characteristics may be attributed to more favorable conditions of electric field during programming, i.e. during charging of the floating gate, in respect to those existing in the case of the conventional n-channel memory cell.

摘要翻译： 使用根据现有技术的通常使用p沟道MOS器件代替n沟道MOS器件的非易失性EPROM型存储单元提供了几个优点：改进的编程特性，用于写入的相对较低的栅极电压，较低的 功耗以及绝大多数CMOS制造工艺的兼容性。 关于这种令人惊奇的特性的解释可以归因于在编程期间，即在对浮动栅极充电期间相对于在常规n沟道存储单元的情况下存在的电场的更有利的条件。

公开(公告)号：US4808261A

公开(公告)日：1989-02-28

申请号：US40152

申请日：1987-04-20

申请人： Gabriella Ghidini ,  Giuseppe Crisenza

发明人： Gabriella Ghidini ,  Giuseppe Crisenza

IPC分类号： H01L21/8247 ,  H01L21/28 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/306 ,  B44C1/22 ,  C03C15/00 ,  C03C25/06

CPC分类号： H01L21/28273 ,  H01L27/115

摘要： The process calls for covering of the dielectric with a thin additional layer of polysilicon which has the function of protecting the dielectric from any defects which would otherwise be introduced from the subsequent masking.

摘要翻译： 该方法要求用薄的附加多晶硅层覆盖电介质，该多晶硅附加层具有保护电介质不会从随后的掩模引入的任何缺陷的功能。

公开(公告)号：US4799021A

公开(公告)日：1989-01-17

申请号：US73654

申请日：1987-07-15

申请人： Lucio Cozzi

发明人： Lucio Cozzi

IPC分类号： H01L27/10 ,  G01R31/26 ,  G01R31/28 ,  G01R31/30 ,  G11C29/00 ,  G11C29/06 ,  G11C29/50 ,  H01L21/66 ,  H01L21/8247 ,  H01L29/788 ,  H01L29/792 ,  G01R1/04 ,  G01R31/00

CPC分类号： G01R31/2868 ,  G01R31/2642 ,  G11C29/50 ,  G11C29/50012 ,  G11C29/50016 ,  G11C16/04

摘要： An apparatus and a relative method which permit carrying out a complete cycle of functional tests and parametric measurements on EPROM type semiconductor devices during their permanence inside a burn-in chamber, thus greatly reducing the time necessary for testing and classifying the devices, besides ensuring a higher reliability. The system utilizes special "intelligent" cards, i.e. provided with a card microprocessor which may be connected to a supervisory system's CPU directing the test and classification process of the devices.

摘要翻译： 一种装置和相对方法，其允许在EPROM型半导体器件在老化室内的永久性期间执行功能测试和参数测量的完整循环，从而大大减少了测试和分类器件所需的时间，另外确保 更高的可靠性。 该系统使用特殊的“智能”卡，即设置有卡微处理器，其可以连接到指示设备的测试和分类处理的监督系统的CPU。