-
1.发明授权
公开(公告)号：US5709805A
公开(公告)日：1998-01-20
申请号：US755527
申请日：1996-11-20
IPC分类号： H05K1/05 , H05K3/00 , H05K3/30 , H05K3/38 , H05K3/42 , H05K3/44 , H05K3/46 , B44C1/22 , C23F1/00
CPC分类号： H05K3/445 , H05K3/386 , H05K3/4623 , H05K3/4641 , H05K1/056 , H05K2201/015 , H05K2201/0195 , H05K2201/0209 , H05K2201/0355 , H05K2201/068 , H05K3/002 , H05K3/305 , H05K3/427 , H05K3/429 , H05K3/4626 , Y10S428/901 , Y10T428/24917 , Y10T428/249982 , Y10T428/249984 , Y10T428/249986 , Y10T428/2804 , Y10T428/3154
摘要： A method for producing a panel of a multi-layer electronic circuit package and resulting article of manufacture is provided comprising the steps of coating a circuitized core material that has been cut into panels with a dielectric material and copper cover sheets; forming circuits from the cover sheets by etching; applying an adhesive polymer across the dielectric material covering the entire area of the panel; applying a cover sheet; drilling the panel to form through-holes and vias; seeding and plating the through-holes and vias with joining metal; applying photo-resist to the panels exposed with an image of the area of the panel to be joined and developed; and etching the cover sheet and the photo-resist away in the area of the panel to be joined to expose the adhesive polymer.
摘要翻译： 提供一种多层电子电路封装的面板的制造方法及其制造方法，其特征在于包括以下步骤：利用电介质材料和铜覆盖层将被切割成电路的芯材涂覆在板上; 通过蚀刻从覆盖片形成电路; 在覆盖面板的整个区域的电介质材料上施加粘合剂聚合物; 应用封面; 钻孔板形成通孔和通孔; 用连接金属对通孔和通孔进行接种和电镀; 对要接合和显影的面板区域的图像曝光的面板施加光致抗蚀剂; 并且在要接合的面板的区域中蚀刻覆盖片和光致抗蚀剂以暴露粘合聚合物。
-
公开(公告)号：US5872337A
公开(公告)日：1999-02-16
申请号：US711240
申请日：1996-09-09
申请人： Donald Seton Farquhar , Stephen Joseph Fuerniss , Charles Robert Davis , David Lee Questad , Darbha Suryanarayana , Jeffrey Alan Zimmerman
发明人： Donald Seton Farquhar , Stephen Joseph Fuerniss , Charles Robert Davis , David Lee Questad , Darbha Suryanarayana , Jeffrey Alan Zimmerman
IPC分类号： H01L23/538 , H05K1/00 , H05K3/00
CPC分类号： H05K1/0281 , H01L23/5387 , H05K3/4691 , H01L2924/0002 , H05K2201/09109 , H05K2201/2009
摘要： Reinforcement members are disposed along only the transverse edge regions of selected flexible cables of an integral chip carrier and cable assembly, and along only the respectively aligned end areas of the chip carrier portion of the assembly. The reinforcement members may be disposed along all of the flexible cables and end areas of the assembly, or on only selected cable and end area portions of the assembly. The reinforcement members are formed of a tough tear resistant polymer material, such as a hot melt adhesive or polymer tape or film.
摘要翻译： 加强构件仅沿着整体芯片载体和电缆组件的选定柔性电缆的横向边缘区域布置，并且仅沿着组件的芯片承载部分的相应对准的端部区域布置。 加强构件可以沿着组件的所有柔性电缆和端部区域，或仅在组件的所选择的电缆和端部区域部分设置。 加强构件由坚韧的抗撕裂聚合物材料形成，例如热熔粘合剂或聚合物带或膜。
-
3.发明授权
公开(公告)号：US5679444A
公开(公告)日：1997-10-21
申请号：US679874
申请日：1996-07-15
IPC分类号： H05K1/05 , H05K3/00 , H05K3/30 , H05K3/38 , H05K3/42 , H05K3/44 , H05K3/46 , B32B3/00 , B32B5/12 , B32B5/22 , H05K1/03
CPC分类号： H05K3/445 , H05K3/386 , H05K3/4623 , H05K3/4641 , H05K1/056 , H05K2201/015 , H05K2201/0195 , H05K2201/0209 , H05K2201/0355 , H05K2201/068 , H05K3/002 , H05K3/305 , H05K3/427 , H05K3/429 , H05K3/4626 , Y10S428/901 , Y10T428/24917 , Y10T428/249982 , Y10T428/249984 , Y10T428/249986 , Y10T428/2804 , Y10T428/3154
摘要： A method for producing a panel of a multi-layer electronic circuit package and resulting article of manufacture is provided comprising the steps of coating a circuitized core material that has been cut into panels with a dielectric material and copper cover sheets; forming circuits from the cover sheets by etching; applying an adhesive polymer across the dielectric material covering the entire area of the panel; applying a cover sheet; drilling the panel to form through-holes and vias; seeding and plating the through-holes and vias with joining metal; applying photo-resist to the panels exposed with an image of the area of the panel to be joined and developed; and etching the cover sheet and the photo-resist away in the area of the panel to be joined to expose the adhesive polymer.
摘要翻译： 提供一种多层电子电路封装的面板的制造方法及其制造方法，其特征在于包括以下步骤：利用电介质材料和铜覆盖层将被切割成电路的芯材涂覆在板上; 通过蚀刻从覆盖片形成电路; 在覆盖面板的整个区域的电介质材料上施加粘合剂聚合物; 应用封面; 钻孔板形成通孔和通孔; 用连接金属对通孔和通孔进行接种和电镀; 对要接合和显影的面板区域的图像曝光的面板施加光致抗蚀剂; 并且在要接合的面板的区域中蚀刻覆盖片和光致抗蚀剂以暴露粘合聚合物。
-
4.发明授权
公开(公告)号：US5789121A
公开(公告)日：1998-08-04
申请号：US879470
申请日：1997-06-20
申请人： Douglas Adam Cywar , Charles Robert Davis , Thomas Patrick Duffy , Frank Daniel Egitto , Paul Joseph Hart , Gerald Walter Jones , Edward McLeskey
发明人： Douglas Adam Cywar , Charles Robert Davis , Thomas Patrick Duffy , Frank Daniel Egitto , Paul Joseph Hart , Gerald Walter Jones , Edward McLeskey
CPC分类号： G03F7/00 , H05K3/0032 , H05K3/1258 , H05K3/4069 , H05K1/095 , H05K2201/015 , H05K2201/0209 , H05K2203/0191 , H05K2203/0568 , H05K2203/0769 , H05K2203/0783 , H05K2203/1383 , H05K3/0035 , H05K3/107 , H05K3/4664 , Y10S428/901 , Y10S430/146 , Y10T428/24917
摘要： The present invention provides a method of ablative photodecomposition and forming metal pattern which attains high resolution, is convenient, and employs non-halogenated solvents. The present invention is directed to a process for forming a metal pattern, preferably circuitization on an organic substrate, preferably on a circuit board or component thereof, which comprises coating the substrate with an ablatively-removable coating comprising a polymer resin preferably an acrylate polymer resin and preferably an ultraviolet absorber. A pattern is formed in the polymer coating corresponding to the desired metal pattern by irradiating at least a portion of the polymer coating with a sufficient amount of ultraviolet radiation to thereby ablatively remove the irradiated portion of the polymer coating. Next the patterned substrate is coated with a conductive metal paste to define the metal pattern, and the conductive metal paste is cured. The remaining polymer coating is removed by solvent stripping with nonhalogenated solvents. The present invention further includes patterning electronic structures comprising multilayer circuitry using the above method. An excimer laser is used to form vias or through holes in the electronic structure while simultaneously patterning the polymer coating. This results in perfect alignment between the pattern formed in the polymer coating and the vias or through holes. High resolution circuitry is thus attainable when the electronic structure is subsequently metallized with a conductive metal paste.
摘要翻译： 本发明提供了一种烧蚀光分解和形成金属图案的方法，其获得高分辨率，方便并采用非卤化溶剂。 本发明涉及一种用于形成金属图案的方法，优选在有机基板上，优选在电路板或其组件上进行电路化，该方法包括用可剥离涂层涂覆基材，该涂层包含聚合物树脂，优选丙烯酸酯聚合物树脂 优选紫外线吸收剂。 通过用足够量的紫外线照射至少一部分聚合物涂层，形成对应于所需金属图案的聚合物涂层中的图案，从而消除聚合物涂层的照射部分。 接下来，用导电金属膏涂覆图案化衬底以限定金属图案，并且导电金属膏被固化。 用非卤化溶剂通过溶剂汽提除去剩余的聚合物涂层。 本发明还包括使用上述方法图案化包括多层电路的电子结构。 准分子激光器用于在电子结构中形成通孔或通孔，同时构图聚合物涂层。 这导致在聚合物涂层中形成的图案与通孔或通孔之间完美对准。 因此，当电子结构随后用导电金属膏进行金属化时，可实现高分辨率电路。
-
公开(公告)号：US07009280B2
公开(公告)日：2006-03-07
申请号：US10709320
申请日：2004-04-28
申请人： Matthew Angyal , Edward Paul Barth , Sanjit Kumar Das , Charles Robert Davis , Habib Hichri , William Francis Landers , Jia Lee
发明人： Matthew Angyal , Edward Paul Barth , Sanjit Kumar Das , Charles Robert Davis , Habib Hichri , William Francis Landers , Jia Lee
IPC分类号： H01L23/58
CPC分类号： H01L23/53295 , C23C16/401 , H01L21/02126 , H01L21/022 , H01L21/02216 , H01L21/02274 , H01L21/02362 , H01L21/31633 , H01L21/76829 , H01L21/76835 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： An interlevel dielectric layer (ILD) comprises a low-k dielectric layer; and a low-k dielectric film, deposited under compressive stress, atop the dielectric layer. The dielectric layer comprises a low-k material, such as an organosilicon glass (OSG) or a SiCOH material. The dielectric film has a thickness, which is 2%–10% of the thickness of the dielectric layer, has a similar chemical composition to the dielectric layer, but has a different morphology than the dielectric layer. The dielectric film is deposited under compressive stress, in situ, at or near the end of the dielectric layer deposition by altering a process that was used to deposit the low-k dielectric layer.
摘要翻译： 层间电介质层（ILD）包括低k电介质层; 以及在压电应力下沉积在电介质层顶上的低k电介质膜。 电介质层包括低k材料，例如有机硅玻璃（OSG）或SiCOH材料。 电介质膜的厚度为电介质层厚度的2％-10％，与电介质层具有相似的化学成分，但具有与电介质层不同的形态。 通过改变用于沉积低k电介质层的工艺，在介电层沉积的结束处或在其附近的压应力下沉积电介质膜。
-
-
-
-
搜索结果
5 条记录 (耗时 0.016 秒)
